Mem: Reclaim some request flags used by MIPS for alignment checking.

[gem5.git] / src / arch / arm / miscregs.cc

diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index e4375fb8a8b2a4568ad1e598d44c9a0f38269c52..fd861befce381fd2db0892a9a7c4ee436c5e9435 100644 (file)
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -35,8 +35,10 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Gabe Black
+ *          Ali Saidi
  */
 
+#include "arch/arm/isa.hh"
 #include "arch/arm/miscregs.hh"
 #include "base/misc.hh"
 
@@ -151,7 +153,7 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
         }
         break;
       case 2:
-        if (opc2 == 0 && crm == 0) {
+        if (opc1 == 0 && crm == 0) {
             switch (opc2) {
               case 0:
                 return MISCREG_TTBR0;
@@ -339,24 +341,48 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
         }
         break;
       case 9:
-        if (opc1 >= 0 && opc1 <= 7) {
+        if (opc1 == 0) {
             switch (crm) {
-              case 0:
-              case 1:
-              case 2:
-              case 5:
-              case 6:
-              case 7:
-              case 8:
-                //Reserved for Branch Predictor, Cache and TCM operations
               case 12:
+                switch (opc2) {
+                  case 0:
+                    return MISCREG_PMCR;
+                  case 1:
+                    return MISCREG_PMCNTENSET;
+                  case 2:
+                    return MISCREG_PMCNTENCLR;
+                  case 3:
+                    return MISCREG_PMOVSR;
+                  case 4:
+                    return MISCREG_PMSWINC;
+                  case 5:
+                    return MISCREG_PMSELR;
+                  case 6:
+                    return MISCREG_PMCEID0;
+                  case 7:
+                    return MISCREG_PMCEID1;
+                }
               case 13:
+                switch (opc2) {
+                  case 0:
+                    return MISCREG_PMCCNTR;
+                  case 1:
+                    return MISCREG_PMC_OTHER;
+                  case 2:
+                    return MISCREG_PMXEVCNTR;
+                }
               case 14:
-              case 15:
-                // Reserved for Performance monitors
-                break;
+                switch (opc2) {
+                  case 0:
+                    return MISCREG_PMUSERENR;
+                  case 1:
+                    return MISCREG_PMINTENSET;
+                  case 2:
+                    return MISCREG_PMINTENCLR;
+                }
             }
         }
+        //Reserved for Branch Predictor, Cache and TCM operations
         break;
       case 10:
         if (opc1 == 0) {
@@ -406,7 +432,7 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
       case 13:
         if (opc1 == 0) {
             if (crm == 0) {
-                switch (crm) {
+                switch (opc2) {
                   case 0:
                     return MISCREG_FCEIDR;
                   case 1: