mem-cache: Add multiple eviction stats

[gem5.git] / src / arch / arm / miscregs.hh

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index feef79e7350d324574a8ef99785efcc978567cfc..4f522f298b8ce05e563ba965fc669516e63c2577 100644 (file)
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2018 ARM Limited
+ * Copyright (c) 2010-2019 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -182,6 +182,7 @@ namespace ArmISA
         MISCREG_HSCTLR,
         MISCREG_HACTLR,
         MISCREG_HCR,
+        MISCREG_HCR2,
         MISCREG_HDCR,
         MISCREG_HCPTR,
         MISCREG_HSTR,
@@ -930,6 +931,9 @@ namespace ArmISA
         MISCREG_VSESR_EL2,
         MISCREG_VDISR_EL2,
 
+        // PSTATE
+        MISCREG_PAN,
+
         // Total number of Misc Registers: Physical + Dummy
         NUM_MISCREGS
     };
@@ -946,6 +950,9 @@ namespace ArmISA
         MISCREG_BANKED,  // True if the register is banked between the two
                          // security states, and this is the parent node of the
                          // two banked registers
+        MISCREG_BANKED64, // True if the register is banked between the two
+                          // security states, and this is the parent node of
+                          // the two banked registers. Used in AA64 only.
         MISCREG_BANKED_CHILD, // The entry is one of the child registers that
                               // forms a banked set of regs (along with the
                               // other child regs)
@@ -1121,6 +1128,7 @@ namespace ArmISA
         "hsctlr",
         "hactlr",
         "hcr",
+        "hcr2",
         "hdcr",
         "hcptr",
         "hstr",
@@ -1854,6 +1862,9 @@ namespace ArmISA
         "disr_el1",
         "vsesr_el2",
         "vdisr_el2",
+
+        // PSTATE
+        "pan",
     };
 
     static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS,
@@ -1935,6 +1946,9 @@ namespace ArmISA
     int
     snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns);
 
+    int
+    snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc);
+
     // Takes a misc reg index and returns the root reg if its one of a set of
     // banked registers
     void