ARM: Break up condition codes into normal flags, saturation, and simd.

[gem5.git] / src / arch / arm / miscregs.hh

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index c506455f86147a2a53c1b1e0e523b7bafb398473..813b98b692ad69b1438a2b233124705511276e3b 100644 (file)
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -269,7 +269,10 @@ namespace ArmISA
 
     // This mask selects bits of the CPSR that actually go in the CondCodes
     // integer register to allow renaming.
-    static const uint32_t CondCodesMask = 0xF80F0000;
+    static const uint32_t CondCodesMask   = 0xF80F0000;
+    static const uint32_t CondCodesMaskF  = 0xF0000000;
+    static const uint32_t CondCodesMaskQ  = 0x08000000;
+    static const uint32_t CondCodesMaskGE = 0x000F0000;
 
     BitUnion32(SCTLR)
         Bitfield<31> ie;  // Instruction endianness