SPARC: Get rid of the copy/pasted StackTrace stolen from Alpha.

[gem5.git] / src / arch / arm / miscregs.hh

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index ddb4ea9343004f1e6cde0a4419bef10002079700..aa3f47419efe8ef402a836a892a108ecde248847 100644 (file)
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -67,6 +67,7 @@ namespace ArmISA
 
     enum MiscRegIndex {
         MISCREG_CPSR = 0,
+        MISCREG_ITSTATE,
         MISCREG_SPSR,
         MISCREG_SPSR_FIQ,
         MISCREG_SPSR_IRQ,
@@ -137,12 +138,36 @@ namespace ArmISA
         MISCREG_CTR,
         MISCREG_SCR,
         MISCREG_SDER,
+        MISCREG_PAR,
+        MISCREG_V2PCWPR,
+        MISCREG_V2PCWPW,
+        MISCREG_V2PCWUR,
+        MISCREG_V2PCWUW,
+        MISCREG_V2POWPR,
+        MISCREG_V2POWPW,
+        MISCREG_V2POWUR,
+        MISCREG_V2POWUW,
+        MISCREG_ID_MMFR0,
+        MISCREG_ACTLR,
+        MISCREG_PMCR,
+        MISCREG_PMCCNTR,
+        MISCREG_PMCNTENSET,
+        MISCREG_PMCNTENCLR,
+        MISCREG_PMOVSR,
+        MISCREG_PMSWINC,
+        MISCREG_PMSELR,
+        MISCREG_PMCEID0,
+        MISCREG_PMCEID1,
+        MISCREG_PMC_OTHER,
+        MISCREG_PMXEVCNTR,
+        MISCREG_PMUSERENR,
+        MISCREG_PMINTENSET,
+        MISCREG_PMINTENCLR,
         MISCREG_CP15_UNIMP_START,
         MISCREG_TCMTR = MISCREG_CP15_UNIMP_START,
         MISCREG_ID_PFR1,
         MISCREG_ID_DFR0,
         MISCREG_ID_AFR0,
-        MISCREG_ID_MMFR0,
         MISCREG_ID_MMFR1,
         MISCREG_ID_MMFR2,
         MISCREG_ID_MMFR3,
@@ -152,9 +177,7 @@ namespace ArmISA
         MISCREG_ID_ISAR3,
         MISCREG_ID_ISAR4,
         MISCREG_ID_ISAR5,
-        MISCREG_PAR,
         MISCREG_AIDR,
-        MISCREG_ACTLR,
         MISCREG_ADFSR,
         MISCREG_AIFSR,
         MISCREG_DCIMVAC,
@@ -162,14 +185,6 @@ namespace ArmISA
         MISCREG_MCCSW,
         MISCREG_DCCMVAU,
         MISCREG_NSACR,
-        MISCREG_V2PCWPR,
-        MISCREG_V2PCWPW,
-        MISCREG_V2PCWUR,
-        MISCREG_V2PCWUW,
-        MISCREG_V2POWPR,
-        MISCREG_V2POWPW,
-        MISCREG_V2POWUR,
-        MISCREG_V2POWUW,
         MISCREG_VBAR,
         MISCREG_MVBAR,
         MISCREG_ISR,
@@ -189,7 +204,7 @@ namespace ArmISA
                                unsigned crm, unsigned opc2);
 
     const char * const miscRegName[NUM_MISCREGS] = {
-        "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
+        "cpsr", "itstate", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
         "spsr_mon", "spsr_und", "spsr_abt",
         "fpsr", "fpsid", "fpscr", "fpexc", "mvfr0", "mvfr1",
         "sctlr_rst", "sev_mailbox",
@@ -205,20 +220,25 @@ namespace ArmISA
         "dtlbiall", "dtlbimva", "dtlbiasid",
         "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa",
         "dfsr", "ifsr", "dfar", "ifar", "mpidr",
-        "prrr", "nmrr",  "ttbcr", "id_pfr0", "ctr"
-        "scr", "sder"
-        // Unimplemented below
+        "prrr", "nmrr",  "ttbcr", "id_pfr0", "ctr",
+        "scr", "sder", "par",
+        "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
+        "v2powpr", "v2powpw", "v2powur", "v2powuw",
+        "id_mmfr0","actlr", "pmcr", "pmcntr",
+        "pmcntenset", "pmcntenclr", "pmovsr",
+        "pmswinc", "pmselr", "pmceid0",
+        "pmceid1", "pmc_other", "pmxevcntr",
+        "pmuserenr", "pmintenset", "pmintenclr",
+         // Unimplemented below
         "tcmtr",
         "id_pfr1", "id_dfr0", "id_afr0",
-        "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
+        "id_mmfr1", "id_mmfr2", "id_mmfr3",
         "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
-        "par", "aidr", "actlr",
+        "aidr",
         "adfsr", "aifsr",
         "dcimvac", "dcisw", "mccsw",
         "dccmvau",
         "nsacr",
-        "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
-        "v2powpr", "v2powpw", "v2powur", "v2powuw",
         "vbar", "mvbar", "isr", "fceidr",
         "nop", "raz"
     };
@@ -241,6 +261,14 @@ namespace ArmISA
         Bitfield<4, 0> mode;
     EndBitUnion(CPSR)
 
+    BitUnion8(ITSTATE)
+        Bitfield<7, 4> cond;
+        Bitfield<3, 0> mask;
+        // Bitfields for moving to/from CPSR
+        Bitfield<7, 2> top6;
+        Bitfield<1, 0> bottom2;
+    EndBitUnion(ITSTATE)
+
     // This mask selects bits of the CPSR that actually go in the CondCodes
     // integer register to allow renaming.
     static const uint32_t CondCodesMask = 0xF80F0000;
@@ -326,6 +354,16 @@ namespace ArmISA
         Bitfield<31> n;
     EndBitUnion(FPSCR)
 
+    // This mask selects bits of the FPSCR that actually go in the FpCondCodes
+    // integer register to allow renaming.
+    static const uint32_t FpCondCodesMask = 0xF800009F;
+
+    BitUnion32(FPEXC)
+        Bitfield<31> ex;
+        Bitfield<30> en;
+        Bitfield<29, 0> subArchDefined;
+    EndBitUnion(FPEXC)
+
     BitUnion32(MVFR0)
         Bitfield<3, 0> advSimdRegisters;
         Bitfield<7, 4> singlePrecision;