enum MiscRegIndex {
MISCREG_CPSR = 0,
+ MISCREG_ITSTATE,
MISCREG_SPSR,
MISCREG_SPSR_FIQ,
MISCREG_SPSR_IRQ,
MISCREG_FPEXC,
MISCREG_MVFR0,
MISCREG_MVFR1,
+ MISCREG_SCTLR_RST,
MISCREG_SEV_MAILBOX,
// CP15 registers
MISCREG_TLBIMVA,
MISCREG_TLBIASID,
MISCREG_TLBIMVAA,
- MISCREG_CP15_UNIMP_START,
- MISCREG_CTR = MISCREG_CP15_UNIMP_START,
- MISCREG_TCMTR,
+ MISCREG_DFSR,
+ MISCREG_IFSR,
+ MISCREG_DFAR,
+ MISCREG_IFAR,
MISCREG_MPIDR,
+ MISCREG_PRRR,
+ MISCREG_NMRR,
+ MISCREG_TTBCR,
MISCREG_ID_PFR0,
+ MISCREG_CTR,
+ MISCREG_SCR,
+ MISCREG_SDER,
+ MISCREG_PAR,
+ MISCREG_V2PCWPR,
+ MISCREG_V2PCWPW,
+ MISCREG_V2PCWUR,
+ MISCREG_V2PCWUW,
+ MISCREG_V2POWPR,
+ MISCREG_V2POWPW,
+ MISCREG_V2POWUR,
+ MISCREG_V2POWUW,
+ MISCREG_ID_MMFR0,
+ MISCREG_ACTLR,
+ MISCREG_PMCR,
+ MISCREG_PMCCNTR,
+ MISCREG_PMCNTENSET,
+ MISCREG_PMCNTENCLR,
+ MISCREG_PMOVSR,
+ MISCREG_PMSWINC,
+ MISCREG_PMSELR,
+ MISCREG_PMCEID0,
+ MISCREG_PMCEID1,
+ MISCREG_PMC_OTHER,
+ MISCREG_PMXEVCNTR,
+ MISCREG_PMUSERENR,
+ MISCREG_PMINTENSET,
+ MISCREG_PMINTENCLR,
+ MISCREG_CP15_UNIMP_START,
+ MISCREG_TCMTR = MISCREG_CP15_UNIMP_START,
MISCREG_ID_PFR1,
MISCREG_ID_DFR0,
MISCREG_ID_AFR0,
- MISCREG_ID_MMFR0,
MISCREG_ID_MMFR1,
MISCREG_ID_MMFR2,
MISCREG_ID_MMFR3,
MISCREG_ID_ISAR3,
MISCREG_ID_ISAR4,
MISCREG_ID_ISAR5,
- MISCREG_PAR,
MISCREG_AIDR,
- MISCREG_ACTLR,
- MISCREG_DFSR,
- MISCREG_IFSR,
MISCREG_ADFSR,
MISCREG_AIFSR,
- MISCREG_DFAR,
- MISCREG_IFAR,
MISCREG_DCIMVAC,
MISCREG_DCISW,
MISCREG_MCCSW,
MISCREG_DCCMVAU,
- MISCREG_SCR,
- MISCREG_SDER,
MISCREG_NSACR,
- MISCREG_TTBCR,
- MISCREG_V2PCWPR,
- MISCREG_V2PCWPW,
- MISCREG_V2PCWUR,
- MISCREG_V2PCWUW,
- MISCREG_V2POWPR,
- MISCREG_V2POWPW,
- MISCREG_V2POWUR,
- MISCREG_V2POWUW,
- MISCREG_PRRR,
- MISCREG_NMRR,
MISCREG_VBAR,
MISCREG_MVBAR,
MISCREG_ISR,
unsigned crm, unsigned opc2);
const char * const miscRegName[NUM_MISCREGS] = {
- "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
+ "cpsr", "itstate", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
"spsr_mon", "spsr_und", "spsr_abt",
"fpsr", "fpsid", "fpscr", "fpexc", "mvfr0", "mvfr1",
- "sev_mailbox",
+ "sctlr_rst", "sev_mailbox",
"sctlr", "dccisw", "dccimvac", "dccmvac",
"contextidr", "tpidrurw", "tpidruro", "tpidrprw",
"cp15isb", "cp15dsb", "cp15dmb", "cpacr",
"itlbiall", "itlbimva", "itlbiasid",
"dtlbiall", "dtlbimva", "dtlbiasid",
"tlbiall", "tlbimva", "tlbiasid", "tlbimvaa",
- "ctr", "tcmtr", "mpidr",
- "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
- "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
+ "dfsr", "ifsr", "dfar", "ifar", "mpidr",
+ "prrr", "nmrr", "ttbcr", "id_pfr0", "ctr",
+ "scr", "sder", "par",
+ "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
+ "v2powpr", "v2powpw", "v2powur", "v2powuw",
+ "id_mmfr0","actlr", "pmcr", "pmcntr",
+ "pmcntenset", "pmcntenclr", "pmovsr",
+ "pmswinc", "pmselr", "pmceid0",
+ "pmceid1", "pmc_other", "pmxevcntr",
+ "pmuserenr", "pmintenset", "pmintenclr",
+ // Unimplemented below
+ "tcmtr",
+ "id_pfr1", "id_dfr0", "id_afr0",
+ "id_mmfr1", "id_mmfr2", "id_mmfr3",
"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
- "par", "aidr", "actlr",
- "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
+ "aidr",
+ "adfsr", "aifsr",
"dcimvac", "dcisw", "mccsw",
"dccmvau",
- "scr", "sder", "nsacr", "ttbcr",
- "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
- "v2powpr", "v2powpw", "v2powur", "v2powuw",
- "prrr", "nmrr", "vbar", "mvbar", "isr", "fceidr",
+ "nsacr",
+ "vbar", "mvbar", "isr", "fceidr",
"nop", "raz"
};
Bitfield<4, 0> mode;
EndBitUnion(CPSR)
+ BitUnion8(ITSTATE)
+ Bitfield<7, 4> cond;
+ Bitfield<3, 0> mask;
+ // Bitfields for moving to/from CPSR
+ Bitfield<7, 2> top6;
+ Bitfield<1, 0> bottom2;
+ EndBitUnion(ITSTATE)
+
// This mask selects bits of the CPSR that actually go in the CondCodes
// integer register to allow renaming.
static const uint32_t CondCodesMask = 0xF80F0000;
BitUnion32(SCTLR)
+ Bitfield<31> ie; // Instruction endianness
Bitfield<30> te; // Thumb Exception Enable
Bitfield<29> afe; // Access flag enable
Bitfield<28> tre; // TEX Remap bit
Bitfield<27> nmfi;// Non-maskable fast interrupts enable
Bitfield<25> ee; // Exception Endianness bit
Bitfield<24> ve; // Interrupt vectors enable
- Bitfield<23> rao1;// Read as one
+ Bitfield<23> xp; // Extended page table enable bit
Bitfield<22> u; // Alignment (now unused)
Bitfield<21> fi; // Fast interrupts configuration enable
+ Bitfield<19> dz; // Divide by Zero fault enable bit
Bitfield<18> rao2;// Read as one
- Bitfield<17> ha; // Hardware access flag enable
+ Bitfield<17> br; // Background region bit
Bitfield<16> rao3;// Read as one
Bitfield<14> rr; // Round robin cache replacement
Bitfield<13> v; // Base address for exception vectors
Bitfield<12> i; // instruction cache enable
Bitfield<11> z; // branch prediction enable bit
Bitfield<10> sw; // Enable swp/swpb
+ Bitfield<9,8> rs; // deprecated protection bits
Bitfield<6,3> rao4;// Read as one
Bitfield<7> b; // Endianness support (unused)
Bitfield<2> c; // Cache enable bit
Bitfield<30> d32dis;
Bitfield<31> asedis;
EndBitUnion(CPACR)
+
+ BitUnion32(FSR)
+ Bitfield<3, 0> fsLow;
+ Bitfield<7, 4> domain;
+ Bitfield<10> fsHigh;
+ Bitfield<11> wnr;
+ Bitfield<12> ext;
+ EndBitUnion(FSR)
+
+ BitUnion32(FPSCR)
+ Bitfield<0> ioc;
+ Bitfield<1> dzc;
+ Bitfield<2> ofc;
+ Bitfield<3> ufc;
+ Bitfield<4> ixc;
+ Bitfield<7> idc;
+ Bitfield<8> ioe;
+ Bitfield<9> dze;
+ Bitfield<10> ofe;
+ Bitfield<11> ufe;
+ Bitfield<12> ixe;
+ Bitfield<15> ide;
+ Bitfield<18, 16> len;
+ Bitfield<21, 20> stride;
+ Bitfield<23, 22> rMode;
+ Bitfield<24> fz;
+ Bitfield<25> dn;
+ Bitfield<26> ahp;
+ Bitfield<27> qc;
+ Bitfield<28> v;
+ Bitfield<29> c;
+ Bitfield<30> z;
+ Bitfield<31> n;
+ EndBitUnion(FPSCR)
+
+ // This mask selects bits of the FPSCR that actually go in the FpCondCodes
+ // integer register to allow renaming.
+ static const uint32_t FpCondCodesMask = 0xF800009F;
+
+ BitUnion32(FPEXC)
+ Bitfield<31> ex;
+ Bitfield<30> en;
+ Bitfield<29, 0> subArchDefined;
+ EndBitUnion(FPEXC)
+
+ BitUnion32(MVFR0)
+ Bitfield<3, 0> advSimdRegisters;
+ Bitfield<7, 4> singlePrecision;
+ Bitfield<11, 8> doublePrecision;
+ Bitfield<15, 12> vfpExceptionTrapping;
+ Bitfield<19, 16> divide;
+ Bitfield<23, 20> squareRoot;
+ Bitfield<27, 24> shortVectors;
+ Bitfield<31, 28> roundingModes;
+ EndBitUnion(MVFR0)
+
+ BitUnion32(MVFR1)
+ Bitfield<3, 0> flushToZero;
+ Bitfield<7, 4> defaultNaN;
+ Bitfield<11, 8> advSimdLoadStore;
+ Bitfield<15, 12> advSimdInteger;
+ Bitfield<19, 16> advSimdSinglePrecision;
+ Bitfield<23, 20> advSimdHalfPrecision;
+ Bitfield<27, 24> vfpHalfPrecision;
+ Bitfield<31, 28> raz;
+ EndBitUnion(MVFR1)
+
+ BitUnion32(PRRR)
+ Bitfield<1,0> tr0;
+ Bitfield<3,2> tr1;
+ Bitfield<5,4> tr2;
+ Bitfield<7,6> tr3;
+ Bitfield<9,8> tr4;
+ Bitfield<11,10> tr5;
+ Bitfield<13,12> tr6;
+ Bitfield<15,14> tr7;
+ Bitfield<16> ds0;
+ Bitfield<17> ds1;
+ Bitfield<18> ns0;
+ Bitfield<19> ns1;
+ Bitfield<24> nos0;
+ Bitfield<25> nos1;
+ Bitfield<26> nos2;
+ Bitfield<27> nos3;
+ Bitfield<28> nos4;
+ Bitfield<29> nos5;
+ Bitfield<30> nos6;
+ Bitfield<31> nos7;
+ EndBitUnion(PRRR)
+
+ BitUnion32(NMRR)
+ Bitfield<1,0> ir0;
+ Bitfield<3,2> ir1;
+ Bitfield<5,4> ir2;
+ Bitfield<7,6> ir3;
+ Bitfield<9,8> ir4;
+ Bitfield<11,10> ir5;
+ Bitfield<13,12> ir6;
+ Bitfield<15,14> ir7;
+ Bitfield<17,16> or0;
+ Bitfield<19,18> or1;
+ Bitfield<21,20> or2;
+ Bitfield<23,22> or3;
+ Bitfield<25,24> or4;
+ Bitfield<27,26> or5;
+ Bitfield<29,28> or6;
+ Bitfield<31,30> or7;
+ EndBitUnion(NMRR)
+
};
#endif // __ARCH_ARM_MISCREGS_HH__
projects / gem5.git / blobdiff