arch,sim: Convert clone to GuestABI and define a cloneBackwardsFunc.

[gem5.git] / src / arch / arm / nativetrace.cc

diff --git a/src/arch/arm/nativetrace.cc b/src/arch/arm/nativetrace.cc
index d97be88a25d36784d05b43bc21d261a1263d051c..0a0a250c69fc37956a2b46f3db5d9fdb24449e4b 100644 (file)
--- a/src/arch/arm/nativetrace.cc
+++ b/src/arch/arm/nativetrace.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2010-2011, 2014, 2016-2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -36,14 +36,14 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
  */
 
+#include "arch/arm/nativetrace.hh"
+
 #include "arch/arm/isa_traits.hh"
 #include "arch/arm/miscregs.hh"
-#include "arch/arm/nativetrace.hh"
 #include "cpu/thread_context.hh"
+#include "debug/ExecRegDelta.hh"
 #include "params/ArmNativeTrace.hh"
 #include "sim/byteswap.hh"
 
@@ -53,7 +53,11 @@ namespace Trace {
 static const char *regNames[] = {
     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
     "r8", "r9", "r10", "fp", "r12", "sp", "lr", "pc",
-    "cpsr"
+    "cpsr", "f0", "f1", "f2", "f3", "f4", "f5", "f6",
+    "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14",
+    "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22",
+    "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30",
+    "f31", "fpscr"
 };
 #endif
 
@@ -66,9 +70,9 @@ Trace::ArmNativeTrace::ThreadState::update(NativeTrace *parent)
 
     memcpy(newState, oldState, sizeof(state[0]));
 
-    uint32_t diffVector;
+    uint64_t diffVector;
     parent->read(&diffVector, sizeof(diffVector));
-    diffVector = ArmISA::gtoh(diffVector);
+    diffVector = letoh(diffVector);
 
     int changes = 0;
     for (int i = 0; i < STATE_NUMVALS; i++) {
@@ -81,12 +85,12 @@ Trace::ArmNativeTrace::ThreadState::update(NativeTrace *parent)
         diffVector >>= 1;
     }
 
-    uint32_t values[changes];
+    uint64_t values[changes];
     parent->read(values, sizeof(values));
     int pos = 0;
     for (int i = 0; i < STATE_NUMVALS; i++) {
         if (changed[i]) {
-            newState[i] = ArmISA::gtoh(values[pos++]);
+            newState[i] = letoh(values[pos++]);
             changed[i] = (newState[i] != oldState[i]);
         }
     }
@@ -106,13 +110,27 @@ Trace::ArmNativeTrace::ThreadState::update(ThreadContext *tc)
     }
 
     //R15, aliased with the PC
-    newState[STATE_PC] = tc->readNextPC();
+    newState[STATE_PC] = tc->pcState().npc();
     changed[STATE_PC] = (newState[STATE_PC] != oldState[STATE_PC]);
 
     //CPSR
-    newState[STATE_CPSR] = tc->readMiscReg(MISCREG_CPSR) |
-                           tc->readIntReg(INTREG_CONDCODES);
+    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
+    cpsr.nz = tc->readCCReg(CCREG_NZ);
+    cpsr.c = tc->readCCReg(CCREG_C);
+    cpsr.v = tc->readCCReg(CCREG_V);
+    cpsr.ge = tc->readCCReg(CCREG_GE);
+
+    newState[STATE_CPSR] = cpsr;
     changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]);
+
+    for (int i = 0; i < NumVecV7ArchRegs; i++) {
+        auto vec(tc->readVecReg(RegId(VecRegClass,i))
+            .as<uint64_t, MaxSveVecLenInDWords>());
+        newState[STATE_F0 + 2*i] = vec[0];
+        newState[STATE_F0 + 2*i + 1] = vec[1];
+    }
+    newState[STATE_FPSCR] = tc->readMiscRegNoEffect(MISCREG_FPSCR) |
+                            tc->readCCReg(CCREG_FP);
 }
 
 void
@@ -121,7 +139,7 @@ Trace::ArmNativeTrace::check(NativeTraceRecord *record)
     ThreadContext *tc = record->getThread();
     // This area is read only on the target. It can't stop there to tell us
     // what's going on, so we should skip over anything there also.
-    if (tc->readNextPC() > 0xffff0000)
+    if (tc->nextInstAddr() > 0xffff0000)
         return;
     nState.update(this);
     mState.update(tc);
@@ -138,18 +156,23 @@ Trace::ArmNativeTrace::check(NativeTraceRecord *record)
     // Regular int regs
     for (int i = 0; i < STATE_NUMVALS; i++) {
         if (nState.changed[i] || mState.changed[i]) {
-            const char *vergence = "  ";
             bool oldMatch = (mState.oldState[i] == nState.oldState[i]);
             bool newMatch = (mState.newState[i] == nState.newState[i]);
             if (oldMatch && newMatch) {
                 // The more things change, the more they stay the same.
                 continue;
-            } else if (oldMatch && !newMatch) {
+            }
+
+            errorFound = true;
+
+#ifndef NDEBUG
+            const char *vergence = "  ";
+            if (oldMatch && !newMatch) {
                 vergence = "<>";
             } else if (!oldMatch && newMatch) {
                 vergence = "><";
             }
-            errorFound = true;
+
             if (!nState.changed[i]) {
                 DPRINTF(ExecRegDelta, "%s [%5s] "\
                                       "Native:         %#010x         "\
@@ -172,6 +195,7 @@ Trace::ArmNativeTrace::check(NativeTraceRecord *record)
                                       nState.oldState[i], nState.newState[i],
                                       mState.oldState[i], mState.newState[i]);
             }
+#endif
         }
     }
     if (errorFound) {
@@ -192,7 +216,7 @@ Trace::ArmNativeTrace::check(NativeTraceRecord *record)
     }
 }
 
-} /* namespace Trace */
+} // namespace Trace
 
 ////////////////////////////////////////////////////////////////////////
 //
@@ -202,4 +226,4 @@ Trace::ArmNativeTrace *
 ArmNativeTraceParams::create()
 {
     return new Trace::ArmNativeTrace(this);
-};
+}