/*
+ * Copyright (c) 2010-2011, 2014 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2007-2008 The Florida State University
* All rights reserved.
*
#ifndef __ARCH_ARM_REGISTERS_HH__
#define __ARCH_ARM_REGISTERS_HH__
-#include "arch/arm/max_inst_regs.hh"
+#include "arch/arm/generated/max_inst_regs.hh"
#include "arch/arm/intregs.hh"
+#include "arch/arm/ccregs.hh"
#include "arch/arm/miscregs.hh"
namespace ArmISA {
-using ArmISAInst::MaxInstSrcRegs;
+
+// For a predicated instruction, we need all the
+// destination registers to also be sources
+const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs +
+ ArmISAInst::MaxInstSrcRegs;
using ArmISAInst::MaxInstDestRegs;
+using ArmISAInst::MaxMiscDestRegs;
typedef uint16_t RegIndex;
// cop-0/cop-1 system control register
typedef uint64_t MiscReg;
+// condition code register; must be at least 32 bits for FpCondCodes
+typedef uint64_t CCReg;
+
// Constants Related to the number of registers
const int NumIntArchRegs = NUM_ARCH_INTREGS;
// The number of single precision floating point registers
-const int NumFloatArchRegs = 64;
-const int NumFloatSpecialRegs = 8;
+const int NumFloatV7ArchRegs = 64;
+const int NumFloatV8ArchRegs = 128;
+const int NumFloatSpecialRegs = 32;
const int NumIntRegs = NUM_INTREGS;
-const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
-
+const int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs;
+const int NumCCRegs = NUM_CCREGS;
const int NumMiscRegs = NUM_MISCREGS;
+#define ISA_HAS_CC_REGS
+
+const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
// semantically meaningful register indices
const int ReturnValueReg = 0;
const int ReturnValueReg1 = 1;
const int ReturnValueReg2 = 2;
+const int NumArgumentRegs = 4;
+const int NumArgumentRegs64 = 8;
const int ArgumentReg0 = 0;
const int ArgumentReg1 = 1;
const int ArgumentReg2 = 2;
const int SyscallSuccessReg = ReturnValueReg;
// These help enumerate all the registers for dependence tracking.
-const int FP_Base_DepTag = NumIntRegs * (MODE_MAXMODE + 1);
-const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
+const int FP_Reg_Base = NumIntRegs * (MODE_MAXMODE + 1);
+const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs;
+const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs;
+const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
typedef union {
IntReg intreg;
FloatReg fpreg;
+ CCReg ccreg;
MiscReg ctrlreg;
} AnyReg;