mem-cache: Add multiple eviction stats

[gem5.git] / src / arch / arm / remote_gdb.hh

diff --git a/src/arch/arm/remote_gdb.hh b/src/arch/arm/remote_gdb.hh
index a6b2b9d35dd7cd9d03890564537bf839193cd609..e52ed663ab0062ec41d33bc9429113b4418d8f77 100644 (file)
--- a/src/arch/arm/remote_gdb.hh
+++ b/src/arch/arm/remote_gdb.hh
@@ -1,5 +1,7 @@
 /*
- * Copyright (c) 2013 ARM Limited
+ * Copyright 2015 LabWare
+ * Copyright 2014 Google, Inc.
+ * Copyright (c) 2013, 2016, 2018-2019 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -40,11 +42,17 @@
  *
  * Authors: Nathan Binkert
  *          Stephen Hines
+ *          Boris Shingarov
  */
 
 #ifndef __ARCH_ARM_REMOTE_GDB_HH__
 #define __ARCH_ARM_REMOTE_GDB_HH__
 
+#include <algorithm>
+
+#include "arch/arm/registers.hh"
+#include "arch/arm/utility.hh"
+#include "base/compiler.hh"
 #include "base/remote_gdb.hh"
 
 class System;
@@ -53,42 +61,70 @@ class ThreadContext;
 namespace ArmISA
 {
 
-// AArch32 registers with vfpv3/neon
-const int NUMREGS   = 41;  /* r0-r15, cpsr, d0-d31, fpscr */
-const int REG_R0 = 0;
-const int REG_F0 = 8;
-const int REG_CPSR  = 8;   /* bit 512 to bit 543  */
-const int REG_FPSCR = 40;  /* bit 2592 to bit 2623 */
-
-// AArch64 registers
-const int NUMREGS_64 = 98;  // x0-x31, pc, cpsr (64-bit GPRs)
-                            // v0-v31 (128-bit FPRs)
-const int REG_X0 = 0;
-const int REG_PC_64 = 32;
-const int REG_CPSR_64 = 33;
-const int REG_V0 = 34;
-
-const int MAX_NUMREGS = NUMREGS_64;
-
 class RemoteGDB : public BaseRemoteGDB
 {
+  protected:
+    bool acc(Addr addr, size_t len);
 
-protected:
-  Addr notTakenBkpt;
-  Addr takenBkpt;
-
-protected:
-  bool acc(Addr addr, size_t len);
-  bool write(Addr addr, size_t size, const char *data);
+    class AArch32GdbRegCache : public BaseGdbRegCache
+    {
+      using BaseGdbRegCache::BaseGdbRegCache;
+      private:
+        struct {
+          uint32_t gpr[16];
+          uint32_t cpsr;
+          uint64_t fpr[32];
+          uint32_t fpscr;
+        } M5_ATTR_PACKED r;
+      public:
+        char *data() const { return (char *)&r; }
+        size_t size() const { return sizeof(r); }
+        void getRegs(ThreadContext*);
+        void setRegs(ThreadContext*) const;
+        const std::string
+        name() const
+        {
+            return gdb->name() + ".AArch32GdbRegCache";
+        }
+    };
 
-  void getregs();
-  void setregs();
+    class AArch64GdbRegCache : public BaseGdbRegCache
+    {
+      using BaseGdbRegCache::BaseGdbRegCache;
+      private:
+        struct {
+          uint64_t x[31];
+          uint64_t spx;
+          uint64_t pc;
+          uint32_t cpsr;
+          VecElem v[NumVecV8ArchRegs * NumVecElemPerNeonVecReg];
+          uint32_t fpsr;
+          uint32_t fpcr;
+        } M5_ATTR_PACKED r;
+      public:
+        char *data() const { return (char *)&r; }
+        size_t size() const { return sizeof(r); }
+        void getRegs(ThreadContext*);
+        void setRegs(ThreadContext*) const;
+        const std::string
+        name() const
+        {
+            return gdb->name() + ".AArch64GdbRegCache";
+        }
+    };
 
-  void clearSingleStep();
-  void setSingleStep();
+    AArch32GdbRegCache regCache32;
+    AArch64GdbRegCache regCache64;
 
-public:
-  RemoteGDB(System *_system, ThreadContext *tc);
+  public:
+    RemoteGDB(System *_system, ThreadContext *tc, int _port);
+    BaseGdbRegCache *gdbRegs();
+    std::vector<std::string>
+    availableFeatures() const
+    {
+        return {"qXfer:features:read+"};
+    };
+    bool getXferFeaturesRead(const std::string &annex, std::string &output);
 };
 } // namespace ArmISA