/*
+ * Copyright 2015 LabWare
+ * Copyright 2014 Google, Inc.
+ * Copyright (c) 2013, 2016, 2018-2019 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* Copyright (c) 2007-2008 The Florida State University
* All rights reserved.
*
* Authors: Nathan Binkert
* Stephen Hines
+ * Boris Shingarov
*/
#ifndef __ARCH_ARM_REMOTE_GDB_HH__
#define __ARCH_ARM_REMOTE_GDB_HH__
+#include <algorithm>
+
+#include "arch/arm/registers.hh"
+#include "arch/arm/utility.hh"
+#include "base/compiler.hh"
#include "base/remote_gdb.hh"
+class System;
+class ThreadContext;
+
namespace ArmISA
{
- class RemoteGDB : public BaseRemoteGDB
- {
- public:
- //These needs to be written to suit ARM
- RemoteGDB(System *system, ThreadContext *context)
- : BaseRemoteGDB(system, context, 1)
- {}
-
- bool acc(Addr, size_t)
- { panic("acc not implemented for ARM!"); }
+class RemoteGDB : public BaseRemoteGDB
+{
+ protected:
+ bool acc(Addr addr, size_t len);
- void getregs()
- { panic("getregs not implemented for ARM!"); }
+ class AArch32GdbRegCache : public BaseGdbRegCache
+ {
+ using BaseGdbRegCache::BaseGdbRegCache;
+ private:
+ struct {
+ uint32_t gpr[16];
+ uint32_t cpsr;
+ uint64_t fpr[32];
+ uint32_t fpscr;
+ } M5_ATTR_PACKED r;
+ public:
+ char *data() const { return (char *)&r; }
+ size_t size() const { return sizeof(r); }
+ void getRegs(ThreadContext*);
+ void setRegs(ThreadContext*) const;
+ const std::string
+ name() const
+ {
+ return gdb->name() + ".AArch32GdbRegCache";
+ }
+ };
- void setregs()
- { panic("setregs not implemented for ARM!"); }
+ class AArch64GdbRegCache : public BaseGdbRegCache
+ {
+ using BaseGdbRegCache::BaseGdbRegCache;
+ private:
+ struct {
+ uint64_t x[31];
+ uint64_t spx;
+ uint64_t pc;
+ uint32_t cpsr;
+ VecElem v[NumVecV8ArchRegs * NumVecElemPerNeonVecReg];
+ uint32_t fpsr;
+ uint32_t fpcr;
+ } M5_ATTR_PACKED r;
+ public:
+ char *data() const { return (char *)&r; }
+ size_t size() const { return sizeof(r); }
+ void getRegs(ThreadContext*);
+ void setRegs(ThreadContext*) const;
+ const std::string
+ name() const
+ {
+ return gdb->name() + ".AArch64GdbRegCache";
+ }
+ };
- void clearSingleStep()
- { panic("clearSingleStep not implemented for ARM!"); }
+ AArch32GdbRegCache regCache32;
+ AArch64GdbRegCache regCache64;
- void setSingleStep()
- { panic("setSingleStep not implemented for ARM!"); }
+ public:
+ RemoteGDB(System *_system, ThreadContext *tc, int _port);
+ BaseGdbRegCache *gdbRegs();
+ std::vector<std::string>
+ availableFeatures() const
+ {
+ return {"qXfer:features:read+"};
};
-}
+ bool getXferFeaturesRead(const std::string &annex, std::string &output);
+};
+} // namespace ArmISA
#endif /* __ARCH_ARM_REMOTE_GDB_H__ */