arch-arm: Fix SoftwareStep::debugExceptionReturnSS

[gem5.git] / src / arch / arm / self_debug.cc

diff --git a/src/arch/arm/self_debug.cc b/src/arch/arm/self_debug.cc
index ef6ad63225a73e705a5b315defd39fe49ce7bc49..21ad84c3717f46d06b60d81f1fef7fb51a8c1915 100644 (file)
--- a/src/arch/arm/self_debug.cc
+++ b/src/arch/arm/self_debug.cc
@@ -643,7 +643,7 @@ WatchPoint::compareAddress(ThreadContext *tc, Addr in_addr, uint8_t bas,
 
 bool
 SoftwareStep::debugExceptionReturnSS(ThreadContext *tc, CPSR spsr,
-                                     ExceptionLevel dest, bool aarch32)
+                                     ExceptionLevel dest)
 {
     bool SS_bit = false;
     bool enabled_src = false;
@@ -652,9 +652,7 @@ SoftwareStep::debugExceptionReturnSS(ThreadContext *tc, CPSR spsr,
 
         bool enabled_dst = false;
         bool secure = isSecureBelowEL3(tc) || dest == EL3;
-//        CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
-//        if (cpsr.width) {
-        if (ELIs32(tc, dest)) {
+        if (spsr.width) {
             enabled_dst = conf->isDebugEnabledForEL32(tc, dest, secure,
                                                       spsr.d == 1);
         } else {