mem-cache: Add multiple eviction stats

[gem5.git] / src / arch / arm / stage2_mmu.hh

diff --git a/src/arch/arm/stage2_mmu.hh b/src/arch/arm/stage2_mmu.hh
old mode 100755 (executable)
new mode 100644 (file)
index 37eca4f..69f2f52
--- a/src/arch/arm/stage2_mmu.hh
+++ b/src/arch/arm/stage2_mmu.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2013 ARM Limited
+ * Copyright (c) 2012-2013, 2015 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -42,6 +42,7 @@
 
 #include "arch/arm/faults.hh"
 #include "arch/arm/tlb.hh"
+#include "dev/dma_device.hh"
 #include "mem/request.hh"
 #include "params/ArmStage2MMU.hh"
 #include "sim/eventq.hh"
@@ -55,18 +56,26 @@ class Stage2MMU : public SimObject
     /** The TLB that will cache the stage 2 look ups. */
     TLB *_stage2Tlb;
 
+  protected:
+
+    /** Port to issue translation requests from */
+    DmaPort port;
+
+    /** Request id for requests generated by this MMU */
+    MasterID masterId;
+
   public:
     /** This translation class is used to trigger the data fetch once a timing
         translation returns the translated physical address */
     class Stage2Translation : public BaseTLB::Translation
     {
       private:
-        uint8_t   *data;
-        int       numBytes;
-        Request   req;
-        Event     *event;
-        Stage2MMU &parent;
-        Addr      oVAddr;
+        uint8_t      *data;
+        int          numBytes;
+        RequestPtr   req;
+        Event        *event;
+        Stage2MMU    &parent;
+        Addr         oVAddr;
 
       public:
         Fault fault;
@@ -78,30 +87,36 @@ class Stage2MMU : public SimObject
         markDelayed() {}
 
         void
-        finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
+        finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc,
                BaseTLB::Mode mode);
 
         void setVirt(Addr vaddr, int size, Request::Flags flags, int masterId)
         {
             numBytes = size;
-            req.setVirt(0, vaddr, size, flags, masterId, 0);
+            req->setVirt(0, vaddr, size, flags, masterId, 0);
         }
 
-        Fault translateTiming(ThreadContext *tc)
+        void translateTiming(ThreadContext *tc)
         {
-            return (parent.stage2Tlb()->translateTiming(&req, tc, this, BaseTLB::Read));
+            parent.stage2Tlb()->translateTiming(req, tc, this, BaseTLB::Read);
         }
     };
 
     typedef ArmStage2MMUParams Params;
     Stage2MMU(const Params *p);
 
+    /**
+     * Get the port that ultimately belongs to the stage-two MMU, but
+     * is used by the two table walkers, and is exposed externally and
+     * connected through the stage-one table walker.
+     */
+    DmaPort& getDMAPort() { return port; }
+
     Fault readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
-        uint8_t *data, int numBytes, Request::Flags flags, int masterId,
-        bool isFunctional);
-    Fault readDataTimed(ThreadContext *tc, Addr descAddr,
-        Stage2Translation *translation, int numBytes, Request::Flags flags,
-        int masterId);
+        uint8_t *data, int numBytes, Request::Flags flags, bool isFunctional);
+    void readDataTimed(ThreadContext *tc, Addr descAddr,
+                       Stage2Translation *translation, int numBytes,
+                       Request::Flags flags);
 
     TLB* stage1Tlb() const { return _stage1Tlb; }
     TLB* stage2Tlb() const { return _stage2Tlb; }