/*
- * Copyright (c) 2012-2013 ARM Limited
+ * Copyright (c) 2012-2013, 2015 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
#include "arch/arm/faults.hh"
#include "arch/arm/tlb.hh"
+#include "dev/dma_device.hh"
#include "mem/request.hh"
#include "params/ArmStage2MMU.hh"
#include "sim/eventq.hh"
/** The TLB that will cache the stage 2 look ups. */
TLB *_stage2Tlb;
+ protected:
+
+ /** Port to issue translation requests from */
+ DmaPort port;
+
+ /** Request id for requests generated by this MMU */
+ MasterID masterId;
+
public:
/** This translation class is used to trigger the data fetch once a timing
translation returns the translated physical address */
markDelayed() {}
void
- finish(Fault fault, RequestPtr req, ThreadContext *tc,
+ finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
BaseTLB::Mode mode);
void setVirt(Addr vaddr, int size, Request::Flags flags, int masterId)
typedef ArmStage2MMUParams Params;
Stage2MMU(const Params *p);
+ /**
+ * Get the port that ultimately belongs to the stage-two MMU, but
+ * is used by the two table walkers, and is exposed externally and
+ * connected through the stage-one table walker.
+ */
+ DmaPort& getPort() { return port; }
+
Fault readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
- uint8_t *data, int numBytes, Request::Flags flags, int masterId,
- bool isFunctional);
+ uint8_t *data, int numBytes, Request::Flags flags, bool isFunctional);
Fault readDataTimed(ThreadContext *tc, Addr descAddr,
- Stage2Translation *translation, int numBytes, Request::Flags flags,
- int masterId);
+ Stage2Translation *translation, int numBytes,
+ Request::Flags flags);
TLB* stage1Tlb() const { return _stage1Tlb; }
TLB* stage2Tlb() const { return _stage2Tlb; }