/*
- * Copyright (c) 2010, 2012-2013, 2015-2016 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2015-2021 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Ali Saidi
*/
#ifndef __ARCH_ARM_SYSTEM_HH__
#include "kern/linux/events.hh"
#include "params/ArmSystem.hh"
-#include "params/GenericArmSystem.hh"
+#include "sim/full_system.hh"
#include "sim/sim_object.hh"
#include "sim/system.hh"
class GenericTimer;
+class BaseGic;
+class FVPBasePwrCtrl;
class ThreadContext;
class ArmSystem : public System
{
protected:
- /**
- * PC based event to skip the dprink() call and emulate its
- * functionality
- */
- Linux::DebugPrintkEvent *debugPrintkEvent;
-
- /** Bootloaders */
- std::vector<std::unique_ptr<ObjectFile>> bootLoaders;
-
- /**
- * Pointer to the bootloader object
- */
- ObjectFile *bootldr;
-
/**
* True if this system implements the Security Extensions
*/
*/
const bool _haveVirtualization;
+ /**
+ * True if this system implements the Crypto Extension
+ */
+ const bool _haveCrypto;
+
/**
* Pointer to the Generic Timer wrapper.
*/
GenericTimer *_genericTimer;
+ BaseGic *_gic;
/**
- * True if the register width of the highest implemented exception level is
- * 64 bits (ARMv8)
+ * Pointer to the Power Controller (if any)
*/
- bool _highestELIs64;
+ FVPBasePwrCtrl *_pwrCtrl;
/**
- * Reset address if the highest implemented exception level is 64 bits
- * (ARMv8)
+ * Reset address (ARMv8)
*/
- const Addr _resetAddr64;
+ Addr _resetAddr;
+
+ /**
+ * True if the register width of the highest implemented exception level is
+ * 64 bits (ARMv8)
+ */
+ bool _highestELIs64;
/**
* Supported physical address range in bits if the highest implemented
*/
const bool _haveLargeAsid64;
- protected:
/**
- * Get a boot loader that matches the kernel.
- *
- * @param obj Kernel binary
- * @return Pointer to boot loader ObjectFile or nullptr if there
- * is no matching boot loader.
+ * True if system implements the transactional memory extension (TME)
*/
- ObjectFile *getBootLoader(ObjectFile *const obj);
+ const bool _haveTME;
- public:
- typedef ArmSystemParams Params;
- const Params *
- params() const
- {
- return dynamic_cast<const Params *>(_params);
- }
+ /**
+ * True if SVE is implemented (ARMv8)
+ */
+ const bool _haveSVE;
- ArmSystem(Params *p);
- ~ArmSystem();
+ /** SVE vector length at reset, in quadwords */
+ const unsigned _sveVL;
/**
- * Initialise the system
+ * True if LSE is implemented (ARMv8.1)
*/
- virtual void initState();
+ const bool _haveLSE;
- virtual Addr fixFuncEventAddr(Addr addr)
+ /** True if FEAT_VHE (Virtualization Host Extensions) is implemented */
+ const bool _haveVHE;
+
+ /** True if Priviledge Access Never is implemented */
+ const unsigned _havePAN;
+
+ /** True if Secure EL2 is implemented */
+ const unsigned _haveSecEL2;
+
+ /**
+ * True if the Semihosting interface is enabled.
+ */
+ ArmSemihosting *const semihosting;
+
+ public:
+ static constexpr Addr PageBytes = ArmISA::PageBytes;
+ static constexpr Addr PageShift = ArmISA::PageShift;
+
+ typedef ArmSystemParams Params;
+ const Params &
+ params() const
{
- // Remove the low bit that thumb symbols have set
- // but that aren't actually odd aligned
- if (addr & 0x1)
- return addr & ~1;
- return addr;
+ return dynamic_cast<const Params &>(_params);
}
+ ArmSystem(const Params &p);
+
/** true if this a multiprocessor system */
bool multiProc;
*/
bool haveVirtualization() const { return _haveVirtualization; }
+ /** Returns true if this system implements the Crypto
+ * Extension
+ */
+ bool haveCrypto() const { return _haveCrypto; }
+
/** Sets the pointer to the Generic Timer. */
- void setGenericTimer(GenericTimer *generic_timer)
+ void
+ setGenericTimer(GenericTimer *generic_timer)
{
_genericTimer = generic_timer;
}
+ /** Sets the pointer to the GIC. */
+ void setGIC(BaseGic *gic) { _gic = gic; }
+
+ /** Sets the pointer to the Power Controller */
+ void setPowerController(FVPBasePwrCtrl *pwr_ctrl)
+ {
+ _pwrCtrl = pwr_ctrl;
+ }
+
/** Get a pointer to the system's generic timer model */
GenericTimer *getGenericTimer() const { return _genericTimer; }
+ /** Get a pointer to the system's GIC */
+ BaseGic *getGIC() const { return _gic; }
+
+ /** Get a pointer to the system's power controller */
+ FVPBasePwrCtrl *getPowerController() const { return _pwrCtrl; }
+
/** Returns true if the register width of the highest implemented exception
* level is 64 bits (ARMv8) */
bool highestELIs64() const { return _highestELIs64; }
/** Returns the highest implemented exception level */
- ExceptionLevel highestEL() const
+ ArmISA::ExceptionLevel
+ highestEL() const
{
if (_haveSecurity)
- return EL3;
+ return ArmISA::EL3;
if (_haveVirtualization)
- return EL2;
- return EL1;
+ return ArmISA::EL2;
+ return ArmISA::EL1;
}
/** Returns the reset address if the highest implemented exception level is
* 64 bits (ARMv8) */
- Addr resetAddr64() const { return _resetAddr64; }
+ Addr resetAddr() const { return _resetAddr; }
+ void setResetAddr(Addr addr) { _resetAddr = addr; }
/** Returns true if ASID is 16 bits in AArch64 (ARMv8) */
bool haveLargeAsid64() const { return _haveLargeAsid64; }
+ /** Returns true if this system implements the transactional
+ * memory extension (ARMv9)
+ */
+ bool haveTME() const { return _haveTME; }
+
+ /** Returns true if SVE is implemented (ARMv8) */
+ bool haveSVE() const { return _haveSVE; }
+
+ /** Returns the SVE vector length at reset, in quadwords */
+ unsigned sveVL() const { return _sveVL; }
+
+ /** Returns true if LSE is implemented (ARMv8.1) */
+ bool haveLSE() const { return _haveLSE; }
+
+ /** Returns true if Virtualization Host Extensions is implemented */
+ bool haveVHE() const { return _haveVHE; }
+
+ /** Returns true if Priviledge Access Never is implemented */
+ bool havePAN() const { return _havePAN; }
+
+ /** Returns true if Priviledge Access Never is implemented */
+ bool haveSecEL2() const { return _haveSecEL2; }
+
/** Returns the supported physical address range in bits if the highest
* implemented exception level is 64 bits (ARMv8) */
uint8_t physAddrRange64() const { return _physAddrRange64; }
/** Returns the supported physical address range in bits */
- uint8_t physAddrRange() const
+ uint8_t
+ physAddrRange() const
{
if (_highestELIs64)
return _physAddrRange64;
}
/** Returns the physical address mask */
- Addr physAddrMask() const
+ Addr physAddrMask() const { return mask(physAddrRange()); }
+
+ /** Is Arm Semihosting support enabled? */
+ bool haveSemihosting() const { return semihosting != nullptr; }
+
+ /**
+ * Returns a valid ArmSystem pointer if using ARM ISA, it fails
+ * otherwise.
+ */
+ static ArmSystem*
+ getArmSystem(ThreadContext *tc)
{
- return mask(physAddrRange());
+ assert(FullSystem);
+ return static_cast<ArmSystem *>(tc->getSystemPtr());
}
/** Returns true if the system of a specific thread context implements the
/** Returns the highest implemented exception level for the system of a
* specific thread context
*/
- static ExceptionLevel highestEL(ThreadContext *tc);
+ static ArmISA::ExceptionLevel highestEL(ThreadContext *tc);
- /** Returns the reset address if the highest implemented exception level for
- * the system of a specific thread context is 64 bits (ARMv8)
+ /** Return true if the system implements a specific exception level */
+ static bool haveEL(ThreadContext *tc, ArmISA::ExceptionLevel el);
+
+ /** Returns true if the system of a specific thread context implements the
+ * transactional memory extension (TME)
*/
- static Addr resetAddr64(ThreadContext *tc);
+ static bool haveTME(ThreadContext *tc);
+
+ /** Returns the reset address if the highest implemented exception level
+ * for the system of a specific thread context is 64 bits (ARMv8)
+ */
+ static Addr resetAddr(ThreadContext *tc);
/** Returns the supported physical address range in bits for the system of a
* specific thread context
/** Returns true if ASID is 16 bits for the system of a specific thread
* context while in AArch64 (ARMv8) */
static bool haveLargeAsid64(ThreadContext *tc);
-};
-class GenericArmSystem : public ArmSystem
-{
- public:
- typedef GenericArmSystemParams Params;
- const Params *
- params() const
- {
- return dynamic_cast<const Params *>(_params);
- }
+ /** Is Arm Semihosting support enabled? */
+ static bool haveSemihosting(ThreadContext *tc);
+
+ /** Make a Semihosting call from aarch64 */
+ static bool callSemihosting64(ThreadContext *tc, bool gem5_ops=false);
- GenericArmSystem(Params *p) : ArmSystem(p) {};
- virtual ~GenericArmSystem() {};
+ /** Make a Semihosting call from aarch32 */
+ static bool callSemihosting32(ThreadContext *tc, bool gem5_ops=false);
+
+ /** Make a Semihosting call from either aarch64 or aarch32 */
+ static bool callSemihosting(ThreadContext *tc, bool gem5_ops=false);
+
+ /** Make a call to notify the power controller of STANDBYWFI assertion */
+ static void callSetStandByWfi(ThreadContext *tc);
+
+ /** Make a call to notify the power controller of STANDBYWFI deassertion */
+ static void callClearStandByWfi(ThreadContext *tc);
/**
- * Initialise the system
+ * Notify the power controller of WAKEREQUEST assertion. Returns true
+ * if WAKEREQUEST is enabled as a power-on mechanism, and the core is now
+ * powered, false otherwise
*/
- virtual void initState();
+ static bool callSetWakeRequest(ThreadContext *tc);
+
+ /** Notify the power controller of WAKEREQUEST deassertion */
+ static void callClearWakeRequest(ThreadContext *tc);
};
#endif
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