/*
- * Copyright (c) 2010, 2012-2013, 2015-2018 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2015-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
const bool _haveLargeAsid64;
/**
- * Range for memory-mapped m5 pseudo ops. The range will be
- * invalid/empty if disabled.
+ * True if SVE is implemented (ARMv8)
*/
- const AddrRange _m5opRange;
+ const bool _haveSVE;
+
+ /** SVE vector length at reset, in quadwords */
+ const unsigned _sveVL;
+
+ /**
+ * True if LSE is implemented (ARMv8.1)
+ */
+ const bool _haveLSE;
+
+ /** True if Priviledge Access Never is implemented */
+ const unsigned _havePAN;
/**
* True if the Semihosting interface is enabled.
/** Returns true if ASID is 16 bits in AArch64 (ARMv8) */
bool haveLargeAsid64() const { return _haveLargeAsid64; }
+ /** Returns true if SVE is implemented (ARMv8) */
+ bool haveSVE() const { return _haveSVE; }
+
+ /** Returns the SVE vector length at reset, in quadwords */
+ unsigned sveVL() const { return _sveVL; }
+
+ /** Returns true if LSE is implemented (ARMv8.1) */
+ bool haveLSE() const { return _haveLSE; }
+
+ /** Returns true if Priviledge Access Never is implemented */
+ bool havePAN() const { return _havePAN; }
+
/** Returns the supported physical address range in bits if the highest
* implemented exception level is 64 bits (ARMv8) */
uint8_t physAddrRange64() const { return _physAddrRange64; }
/** Is Arm Semihosting support enabled? */
bool haveSemihosting() const { return semihosting != nullptr; }
+ /**
+ * Casts the provided System object into a valid ArmSystem, it fails
+ * otherwise.
+ * @param sys System object to cast
+ */
+ static ArmSystem *getArmSystem(System *sys);
+
/**
* Returns a valid ArmSystem pointer if using ARM ISA, it fails
* otherwise.