ARM: Make DataOps select from a set of ways to set the c and v flags.

[gem5.git] / src / arch / arm / tlb.cc

diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index d0cc57a1da328fafb2d3004ee7fe05c2680f53ff..8cce5c1521fa9e5d6d1a7e50f0c0eda214740ef5 100644 (file)
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -29,26 +29,24 @@
  *
  * Authors: Nathan Binkert
  *          Steve Reinhardt
+ *          Jaidev Patwardhan
  *          Stephen Hines
  */
 
 #include <string>
 #include <vector>
 
+#include "arch/arm/faults.hh"
 #include "arch/arm/pagetable.hh"
 #include "arch/arm/tlb.hh"
-#include "arch/arm/faults.hh"
 #include "arch/arm/utility.hh"
 #include "base/inifile.hh"
 #include "base/str.hh"
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
-#include "sim/process.hh"
 #include "mem/page_table.hh"
-#include "params/ArmDTB.hh"
-#include "params/ArmITB.hh"
 #include "params/ArmTLB.hh"
-#include "params/ArmUTB.hh"
+#include "sim/process.hh"
 
 
 using namespace std;
@@ -149,7 +147,7 @@ TLB::checkCacheability(RequestPtr &req)
   // or by the TLB entry
   if((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
     // mark request as uncacheable
-    req->setFlags(req->getFlags() | UNCACHEABLE);
+    req->setFlags(req->getFlags() | Request::UNCACHEABLE);
   }
   return NoFault;
 }
@@ -278,7 +276,7 @@ TLB::regStats()
 }
 
 Fault
-ITB::translate(RequestPtr &req, ThreadContext *tc)
+TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
 {
 #if !FULL_SYSTEM
     Process * p = tc->getProcessPtr();
@@ -289,51 +287,18 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
 
     return NoFault;
 #else
-  fatal("ITB translate not yet implemented\n");
+  fatal("translate atomic not yet implemented\n");
 #endif
 }
 
-Fault
-DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
+void
+TLB::translateTiming(RequestPtr req, ThreadContext *tc,
+        Translation *translation, Mode mode)
 {
-#if !FULL_SYSTEM
-    Process * p = tc->getProcessPtr();
-
-    Fault fault = p->pTable->translate(req);
-    if(fault != NoFault)
-        return fault;
-
-    return NoFault;
-#else
-  fatal("DTB translate not yet implemented\n");
-#endif
+    assert(translation);
+    translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
 }
 
-///////////////////////////////////////////////////////////////////////
-//
-//  Arm ITB
-//
-ITB::ITB(const Params *p)
-    : TLB(p)
-{}
-
-
-///////////////////////////////////////////////////////////////////////
-//
-//  Arm DTB
-//
-DTB::DTB(const Params *p)
-    : TLB(p)
-{}
-
-///////////////////////////////////////////////////////////////////////
-//
-//  Arm UTB
-//
-UTB::UTB(const Params *p)
-    : ITB(p), DTB(p)
-{}
-
 ArmISA::PTE &
 TLB::index(bool advance)
 {
@@ -345,20 +310,8 @@ TLB::index(bool advance)
     return *pte;
 }
 
-ArmISA::ITB *
-ArmITBParams::create()
-{
-    return new ArmISA::ITB(this);
-}
-
-ArmISA::DTB *
-ArmDTBParams::create()
-{
-    return new ArmISA::DTB(this);
-}
-
-ArmISA::UTB *
-ArmUTBParams::create()
+ArmISA::TLB *
+ArmTLBParams::create()
 {
-    return new ArmISA::UTB(this);
+    return new ArmISA::TLB(this);
 }