stage2Mmu(NULL), rangeMRU(1),
aarch64(false), aarch64EL(EL0), isPriv(false), isSecure(false),
isHyp(false), asid(0), vmid(0), dacr(0),
- miscRegValid(false), curTranType(NormalTran)
+ miscRegValid(false), miscRegContext(0), curTranType(NormalTran)
{
tableWalker->setTlb(this);
// than rangeMRU
if (x > rangeMRU && !functional) {
TlbEntry tmp_entry = table[x];
- for(int i = x; i > 0; i--)
+ for (int i = x; i > 0; i--)
table[i] = table[i - 1];
table[0] = tmp_entry;
retval = &table[0];
int num_entries = size;
SERIALIZE_SCALAR(num_entries);
- for(int i = 0; i < size; i++)
+ for (int i = 0; i < size; i++)
table[i].serializeSection(cp, csprintf("TlbEntry%d", i));
}
int num_entries;
UNSERIALIZE_SCALAR(num_entries);
- for(int i = 0; i < min(size, num_entries); i++)
+ for (int i = 0; i < min(size, num_entries); i++)
table[i].unserializeSection(cp, csprintf("TlbEntry%d", i));
}
"flags %#x tranType 0x%x\n", vaddr_tainted, mode, isStage2,
scr, sctlr, flags, tranType);
- // If this is a clrex instruction, provide a PA of 0 with no fault
- // This will force the monitor to set the tracked address to 0
- // a bit of a hack but this effectively clrears this processors monitor
- if (flags & Request::CLEAR_LL){
- // @todo: check implications of security extensions
- req->setPaddr(0);
- req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
- req->setFlags(Request::CLEAR_LL);
- return NoFault;
- }
if ((req->isInstFetch() && (!sctlr.i)) ||
((!req->isInstFetch()) && (!sctlr.c))){
req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
// check if the regs have changed, or the translation mode is different.
// NOTE: the tran type doesn't affect stage 2 TLB's as they only handle
// one type of translation anyway
- if (miscRegValid && ((tranType == curTranType) || isStage2)) {
+ if (miscRegValid && miscRegContext == tc->contextId() &&
+ ((tranType == curTranType) || isStage2)) {
return;
}
}
}
miscRegValid = true;
+ miscRegContext = tc->contextId();
curTranType = tranType;
}