stats: update stats for mmap() change.

[gem5.git] / src / arch / arm / tlb.cc

diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index aee6a251a44c7580630cfe0ade7488a8e236a28d..bdcb91facc8b5847a8cca889307a1321d5fbd276 100644 (file)
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -78,7 +78,7 @@ TLB::TLB(const ArmTLBParams *p)
       stage2Mmu(NULL), rangeMRU(1),
       aarch64(false), aarch64EL(EL0), isPriv(false), isSecure(false),
       isHyp(false), asid(0), vmid(0), dacr(0),
-      miscRegValid(false), curTranType(NormalTran)
+      miscRegValid(false), miscRegContext(0), curTranType(NormalTran)
 {
     tableWalker->setTlb(this);
 
@@ -148,7 +148,7 @@ TLB::lookup(Addr va, uint16_t asn, uint8_t vmid, bool hyp, bool secure,
             // than rangeMRU
             if (x > rangeMRU && !functional) {
                 TlbEntry tmp_entry = table[x];
-                for(int i = x; i > 0; i--)
+                for (int i = x; i > 0; i--)
                     table[i] = table[i - 1];
                 table[0] = tmp_entry;
                 retval = &table[0];
@@ -394,7 +394,7 @@ TLB::serialize(CheckpointOut &cp) const
 
     int num_entries = size;
     SERIALIZE_SCALAR(num_entries);
-    for(int i = 0; i < size; i++)
+    for (int i = 0; i < size; i++)
         table[i].serializeSection(cp, csprintf("TlbEntry%d", i));
 }
 
@@ -410,7 +410,7 @@ TLB::unserialize(CheckpointIn &cp)
 
     int num_entries;
     UNSERIALIZE_SCALAR(num_entries);
-    for(int i = 0; i < min(size, num_entries); i++)
+    for (int i = 0; i < min(size, num_entries); i++)
         table[i].unserializeSection(cp, csprintf("TlbEntry%d", i));
 }
 
@@ -1204,7 +1204,8 @@ TLB::updateMiscReg(ThreadContext *tc, ArmTranslationType tranType)
     // check if the regs have changed, or the translation mode is different.
     // NOTE: the tran type doesn't affect stage 2 TLB's as they only handle
     // one type of translation anyway
-    if (miscRegValid && ((tranType == curTranType) || isStage2)) {
+    if (miscRegValid && miscRegContext == tc->contextId() &&
+            ((tranType == curTranType) || isStage2)) {
         return;
     }
 
@@ -1300,6 +1301,7 @@ TLB::updateMiscReg(ThreadContext *tc, ArmTranslationType tranType)
         }
     }
     miscRegValid = true;
+    miscRegContext = tc->contextId();
     curTranType  = tranType;
 }