ARM: Make DataOps select from a set of ways to set the c and v flags.

[gem5.git] / src / arch / arm / tlb.hh

diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 59fe1a60dbf73a60e3efdeb2be89e459909c939e..d2c035b31afac3889aa643d39284bd50bfad88c3 100644 (file)
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -43,8 +43,7 @@
 #include "arch/arm/pagetable.hh"
 #include "base/statistics.hh"
 #include "mem/request.hh"
-#include "params/ArmDTB.hh"
-#include "params/ArmITB.hh"
+#include "params/ArmTLB.hh"
 #include "sim/faults.hh"
 #include "sim/tlb.hh"
 
@@ -62,6 +61,12 @@ struct TlbEntry
     TlbEntry() {}
     TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
 
+    void
+    updateVaddr(Addr new_vaddr)
+    {
+        panic("unimplemented");
+    }
+
     Addr pageStart()
     {
         return _pageStart;
@@ -92,14 +97,14 @@ class TLB : public BaseTLB
     void nextnlu() { if (++nlu >= size) nlu = 0; }
     ArmISA::PTE *lookup(Addr vpn, uint8_t asn) const;
 
-    mutable Stats::Scalar<> read_hits;
-    mutable Stats::Scalar<> read_misses;
-    mutable Stats::Scalar<> read_acv;
-    mutable Stats::Scalar<> read_accesses;
-    mutable Stats::Scalar<> write_hits;
-    mutable Stats::Scalar<> write_misses;
-    mutable Stats::Scalar<> write_acv;
-    mutable Stats::Scalar<> write_accesses;
+    mutable Stats::Scalar read_hits;
+    mutable Stats::Scalar read_misses;
+    mutable Stats::Scalar read_acv;
+    mutable Stats::Scalar read_accesses;
+    mutable Stats::Scalar write_hits;
+    mutable Stats::Scalar write_misses;
+    mutable Stats::Scalar write_acv;
+    mutable Stats::Scalar write_accesses;
     Stats::Formula hits;
     Stats::Formula misses;
     Stats::Formula invalids;
@@ -129,6 +134,10 @@ class TLB : public BaseTLB
 
     static Fault checkCacheability(RequestPtr &req);
 
+    Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
+    void translateTiming(RequestPtr req, ThreadContext *tc,
+            Translation *translation, Mode mode);
+
     // Checkpointing
     void serialize(std::ostream &os);
     void unserialize(Checkpoint *cp, const std::string &section);
@@ -136,29 +145,6 @@ class TLB : public BaseTLB
     void regStats();
 };
 
-class ITB : public TLB {
-  public:
-    typedef ArmTLBParams Params;
-    ITB(const Params *p);
-
-    Fault translate(RequestPtr &req, ThreadContext *tc);
-};
-
-class DTB : public TLB {
-  public:
-    typedef ArmTLBParams Params;
-    DTB(const Params *p);
-
-    Fault translate(RequestPtr &req, ThreadContext *tc, bool write = false);
-};
-
-class UTB : public ITB, public DTB {
-  public:
-    typedef ArmTLBParams Params;
-    UTB(const Params *p);
-
-};
-
-}
+/* namespace ArmISA */ }
 
 #endif // __ARCH_ARM_TLB_HH__