/*
- * Copyright (c) 2010-2013 ARM Limited
+ * Copyright (c) 2010-2013, 2016, 2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
class TableWalker;
class Stage2LookUp;
class Stage2MMU;
+class TLB;
+
+class TlbTestInterface
+{
+ public:
+ TlbTestInterface() {}
+ virtual ~TlbTestInterface() {}
+
+ /**
+ * Check if a TLB translation should be forced to fail.
+ *
+ * @param req Request requiring a translation.
+ * @param is_priv Access from a privileged mode (i.e., not EL0)
+ * @param mode Access type
+ * @param domain Domain type
+ */
+ virtual Fault translationCheck(const RequestPtr &req, bool is_priv,
+ BaseTLB::Mode mode,
+ TlbEntry::DomainType domain) = 0;
+
+ /**
+ * Check if a page table walker access should be forced to fail.
+ *
+ * @param pa Physical address the walker is accessing
+ * @param size Walker access size
+ * @param va Virtual address that initiated the walk
+ * @param is_secure Access from secure state
+ * @param is_priv Access from a privileged mode (i.e., not EL0)
+ * @param mode Access type
+ * @param domain Domain type
+ * @param lookup_level Page table walker level
+ */
+ virtual Fault walkCheck(Addr pa, Addr size, Addr va, bool is_secure,
+ Addr is_priv, BaseTLB::Mode mode,
+ TlbEntry::DomainType domain,
+ LookupLevel lookup_level) = 0;
+};
class TLB : public BaseTLB
{
HypMode = 0x2,
// Secure code operating as if it wasn't (required by some Address
// Translate operations)
- S1S2NsTran = 0x4
+ S1S2NsTran = 0x4,
+ // Address translation instructions (eg AT S1E0R_Xt) need to be handled
+ // in special ways during translation because they could need to act
+ // like a different EL than the current EL. The following flags are
+ // for these instructions
+ S1E0Tran = 0x8,
+ S1E1Tran = 0x10,
+ S1E2Tran = 0x20,
+ S1E3Tran = 0x40,
+ S12E0Tran = 0x80,
+ S12E1Tran = 0x100
};
+
+ /**
+ * Determine the EL to use for the purpose of a translation given
+ * a specific translation type. If the translation type doesn't
+ * specify an EL, we use the current EL.
+ */
+ static ExceptionLevel tranTypeEL(CPSR cpsr, ArmTranslationType type);
+
protected:
TlbEntry* table; // the Page Table
int size; // TLB Size
bool isStage2; // Indicates this TLB is part of the second stage MMU
bool stage2Req; // Indicates whether a stage 2 lookup is also required
+ // Indicates whether a stage 2 lookup of the table descriptors is required.
+ // Certain address translation instructions will intercept the IPA but the
+ // table descriptors still need to be translated by the stage2.
+ bool stage2DescReq;
uint64_t _attr; // Memory attributes for last accessed TLB entry
bool directToStage2; // Indicates whether all translation requests should
// be routed directly to the stage 2 TLB
TLB *stage2Tlb;
Stage2MMU *stage2Mmu;
+ TlbTestInterface *test;
+
// Access Stats
mutable Stats::Scalar instHits;
mutable Stats::Scalar instMisses;
*/
TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp,
bool secure, bool functional,
- bool ignore_asn, uint8_t target_el);
+ bool ignore_asn, ExceptionLevel target_el);
virtual ~TLB();
- void takeOverFrom(BaseTLB *otlb);
+ void takeOverFrom(BaseTLB *otlb) override;
/// setup all the back pointers
- virtual void init();
+ void init() override;
+
+ void setTestInterface(SimObject *ti);
TableWalker *getTableWalker() { return tableWalker; }
void insert(Addr vaddr, TlbEntry &pte);
- Fault getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode,
+ Fault getTE(TlbEntry **te, const RequestPtr &req,
+ ThreadContext *tc, Mode mode,
Translation *translation, bool timing, bool functional,
bool is_secure, ArmTranslationType tranType);
- Fault getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc,
- Mode mode, Translation *translation, bool timing,
+ Fault getResultTe(TlbEntry **te, const RequestPtr &req,
+ ThreadContext *tc, Mode mode,
+ Translation *translation, bool timing,
bool functional, TlbEntry *mergeTe);
- Fault checkPermissions(TlbEntry *te, RequestPtr req, Mode mode);
- Fault checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode,
+ Fault checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode);
+ Fault checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode,
ThreadContext *tc);
+ bool checkPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req,
+ Mode mode);
/** Reset the entire TLB
* @param secure_lookup if the operation affects the secure world
*/
- void flushAllSecurity(bool secure_lookup, uint8_t target_el,
+ void flushAllSecurity(bool secure_lookup, ExceptionLevel target_el,
bool ignore_el = false);
/** Remove all entries in the non secure world, depending on whether they
* were allocated in hyp mode or not
- * @param hyp if the opperation affects hyp mode
*/
- void flushAllNs(bool hyp, uint8_t target_el, bool ignore_el = false);
+ void flushAllNs(ExceptionLevel target_el, bool ignore_el = false);
/** Reset the entire TLB. Used for CPU switching to prevent stale
* translations after multiple switches
*/
- void flushAll()
+ void flushAll() override
{
- flushAllSecurity(false, 0, true);
- flushAllSecurity(true, 0, true);
+ flushAllSecurity(false, EL0, true);
+ flushAllSecurity(true, EL0, true);
}
/** Remove any entries that match both a va and asn
* @param secure_lookup if the operation affects the secure world
*/
void flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup,
- uint8_t target_el);
+ ExceptionLevel target_el);
/** Remove any entries that match the asn
* @param asn contextid/asn to flush on match
* @param secure_lookup if the operation affects the secure world
*/
- void flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el);
+ void flushAsid(uint64_t asn, bool secure_lookup,
+ ExceptionLevel target_el);
/** Remove all entries that match the va regardless of asn
* @param mva address to flush from cache
* @param secure_lookup if the operation affects the secure world
- * @param hyp if the operation affects hyp mode
*/
- void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el);
+ void flushMva(Addr mva, bool secure_lookup, ExceptionLevel target_el);
- Fault trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain);
- Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec,
- bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level);
+ /**
+ * Invalidate all entries in the stage 2 TLB that match the given ipa
+ * and the current VMID
+ * @param ipa the address to invalidate
+ * @param secure_lookup if the operation affects the secure world
+ */
+ void flushIpaVmid(Addr ipa, bool secure_lookup, ExceptionLevel target_el);
+
+ Fault trickBoxCheck(const RequestPtr &req, Mode mode,
+ TlbEntry::DomainType domain);
+
+ Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz,
+ bool is_exec, bool is_write,
+ TlbEntry::DomainType domain,
+ LookupLevel lookup_level);
void printTlb() const;
- void demapPage(Addr vaddr, uint64_t asn)
+ void demapPage(Addr vaddr, uint64_t asn) override
{
// needed for x86 only
panic("demapPage() is not implemented.\n");
}
- static bool validVirtualAddress(Addr vaddr);
-
/**
* Do a functional lookup on the TLB (for debugging)
* and don't modify any internal state
* Do a functional lookup on the TLB (for checker cpu) that
* behaves like a normal lookup without modifying any page table state.
*/
- Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode,
- ArmTranslationType tranType = NormalTran);
+ Fault translateFunctional(const RequestPtr &req, ThreadContext *tc,
+ Mode mode, ArmTranslationType tranType);
+ Fault
+ translateFunctional(const RequestPtr &req,
+ ThreadContext *tc, Mode mode) override
+ {
+ return translateFunctional(req, tc, mode, NormalTran);
+ }
/** Accessor functions for memory attributes for last accessed TLB entry
*/
return _attr;
}
- Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
+ Fault translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode,
Translation *translation, bool &delay,
bool timing, ArmTranslationType tranType, bool functional = false);
- Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
+ Fault translateSe(const RequestPtr &req, ThreadContext *tc, Mode mode,
Translation *translation, bool &delay, bool timing);
- Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode,
- ArmTranslationType tranType = NormalTran);
- Fault translateTiming(RequestPtr req, ThreadContext *tc,
+ Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode,
+ ArmTranslationType tranType);
+ Fault
+ translateAtomic(const RequestPtr &req,
+ ThreadContext *tc, Mode mode) override
+ {
+ return translateAtomic(req, tc, mode, NormalTran);
+ }
+ void translateTiming(
+ const RequestPtr &req, ThreadContext *tc,
Translation *translation, Mode mode,
- ArmTranslationType tranType = NormalTran);
- Fault translateComplete(RequestPtr req, ThreadContext *tc,
+ ArmTranslationType tranType);
+ void
+ translateTiming(const RequestPtr &req, ThreadContext *tc,
+ Translation *translation, Mode mode) override
+ {
+ translateTiming(req, tc, translation, mode, NormalTran);
+ }
+ Fault translateComplete(const RequestPtr &req, ThreadContext *tc,
Translation *translation, Mode mode, ArmTranslationType tranType,
bool callFromS2);
- Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
+ Fault finalizePhysical(
+ const RequestPtr &req,
+ ThreadContext *tc, Mode mode) const override;
- void drainResume();
+ void drainResume() override;
// Checkpointing
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
- void regStats();
+ void regStats() override;
- void regProbePoints() M5_ATTR_OVERRIDE;
+ void regProbePoints() override;
/**
- * Get the table walker master port. This is used for migrating
+ * Get the table walker port. This is used for migrating
* port connections during a CPU takeOverFrom() call. For
* architectures that do not have a table walker, NULL is
* returned, hence the use of a pointer rather than a
*
* @return A pointer to the walker master port
*/
- virtual BaseMasterPort* getMasterPort();
+ Port *getTableWalkerPort() override;
// Caching misc register values here.
// Writing to misc registers needs to invalidate them.
HCR hcr;
uint32_t dacr;
bool miscRegValid;
+ ContextID miscRegContext;
ArmTranslationType curTranType;
// Cached copies of system-level properties
bool haveVirtualization;
bool haveLargeAsid64;
+ AddrRange m5opRange;
+
void updateMiscReg(ThreadContext *tc,
ArmTranslationType tranType = NormalTran);
* @param mva virtual address to flush
* @param asn contextid/asn to flush on match
* @param secure_lookup if the operation affects the secure world
- * @param hyp if the operation affects hyp mode
* @param ignore_asn if the flush should ignore the asn
*/
void _flushMva(Addr mva, uint64_t asn, bool secure_lookup,
- bool hyp, bool ignore_asn, uint8_t target_el);
-
- bool checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el);
+ bool ignore_asn, ExceptionLevel target_el);
+
+ public: /* Testing */
+ Fault testTranslation(const RequestPtr &req, Mode mode,
+ TlbEntry::DomainType domain);
+ Fault testWalk(Addr pa, Addr size, Addr va, bool is_secure, Mode mode,
+ TlbEntry::DomainType domain,
+ LookupLevel lookup_level);
};
+template<typename T>
+TLB *
+getITBPtr(T *tc)
+{
+ auto tlb = static_cast<TLB *>(tc->getITBPtr());
+ assert(tlb);
+ return tlb;
+}
+
+template<typename T>
+TLB *
+getDTBPtr(T *tc)
+{
+ auto tlb = static_cast<TLB *>(tc->getDTBPtr());
+ assert(tlb);
+ return tlb;
+}
+
} // namespace ArmISA
#endif // __ARCH_ARM_TLB_HH__
projects / gem5.git / blobdiff