ARM: Make DataOps select from a set of ways to set the c and v flags.

[gem5.git] / src / arch / arm / types.hh

diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index 98070a87478bcebc7268e49f1d615fbc694e2d65..3a0fdf2a59c1aa758e2e5e86d33dbd8f67df9446 100644 (file)
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -38,33 +38,24 @@ namespace ArmISA
 {
     typedef uint32_t MachInst;
 
-    BitUnion32(ExtMachInst)
+    BitUnion64(ExtMachInst)
+        // Made up bitfields that make life easier.
+        Bitfield<33>     sevenAndFour;
+        Bitfield<32>     isMisc;
+
         // All the different types of opcode fields.
-        Bitfield<27, 25> opcode;
-        Bitfield<27, 25> opcode27_25;
-        Bitfield<24, 21> opcode24_21;
-        Bitfield<24, 23> opcode24_23;
+        Bitfield<27, 25> encoding;
+        Bitfield<24, 21> opcode;
+        Bitfield<24, 20> mediaOpcode;
         Bitfield<24>     opcode24;
         Bitfield<23, 20> opcode23_20;
         Bitfield<23, 21> opcode23_21;
-        Bitfield<23>     opcode23;
-        Bitfield<22, 8>  opcode22_8;
-        Bitfield<22, 21> opcode22_21;
         Bitfield<22>     opcode22;
-        Bitfield<21, 20> opcode21_20;
-        Bitfield<20>     opcode20;
-        Bitfield<19, 18> opcode19_18;
         Bitfield<19>     opcode19;
         Bitfield<15, 12> opcode15_12;
         Bitfield<15>     opcode15;
-        Bitfield<9>      opcode9;
-        Bitfield<7,  4>  opcode7_4;
-        Bitfield<7,  5>  opcode7_5;
-        Bitfield<7,  6>  opcode7_6;
+        Bitfield<7,  4>  miscOpcode;
         Bitfield<7>      opcode7;
-        Bitfield<6,  5>  opcode6_5;
-        Bitfield<6>      opcode6;
-        Bitfield<5>      opcode5;
         Bitfield<4>      opcode4;
 
         Bitfield<31, 28> condCode;
@@ -77,14 +68,6 @@ namespace ArmISA
 
         Bitfield<11, 8>  rs;
 
-        Bitfield<19, 16> rdup;
-        Bitfield<15, 12> rddn;
-        
-        Bitfield<15, 12> rdhi;
-        Bitfield<11, 8>  rdlo;
-        
-        Bitfield<23>     uField;
-
         SubBitUnion(puswl, 24, 20)
             Bitfield<24> prepost;
             Bitfield<23> up;
@@ -94,72 +77,22 @@ namespace ArmISA
         EndSubBitUnion(puswl)
 
         Bitfield<24, 20> pubwl;
-        Bitfield<24, 20> puiwl;
-        Bitfield<22>     byteAccess;
-
-        Bitfield<23, 20> luas;
 
-        SubBitUnion(imm, 7, 0)
-            Bitfield<7, 4> imm7_4;
-            Bitfield<3, 0> imm3_0;
-        EndSubBitUnion(imm)
-
-        SubBitUnion(msr, 19, 16)
-            Bitfield<19> f;
-            Bitfield<18> s;
-            Bitfield<17> x;
-            Bitfield<16> c;
-        EndSubBitUnion(msr)
-
-        Bitfield<6>      y;
-        Bitfield<5>      x;
-        
-        Bitfield<15, 4>  immed15_4;
-        
-        Bitfield<21>     wField;
+        Bitfield<7, 0> imm;
 
         Bitfield<11, 8>  rotate;
-        Bitfield<7,  0>  immed7_0;
 
-        Bitfield<21>     tField;
         Bitfield<11, 0>  immed11_0;
-
-        Bitfield<20, 16> immed20_16;
-        Bitfield<19, 16> immed19_16;
+        Bitfield<7,  0>  immed7_0;
 
         Bitfield<11, 8>  immedHi11_8;
         Bitfield<3,  0>  immedLo3_0;
-        
-        Bitfield<11, 10> rot;
-
-        Bitfield<5>      rField;
 
-        Bitfield<22>     caret;
         Bitfield<15, 0>  regList;
         
         Bitfield<23, 0>  offset;
-        Bitfield<11, 8>  copro;
-        Bitfield<7,  4>  op1_7_4;
-        Bitfield<3,  0>  cm;
         
-        Bitfield<22>     lField;
-        Bitfield<15, 12> cd;
-        Bitfield<7,  0>  option;
-
-        Bitfield<23, 20> op1_23_20;
-        Bitfield<19, 16> cn;
-        Bitfield<7,  5>  op2_7_5;
-
-        Bitfield<23, 21> op1_23_21;
-
         Bitfield<23, 0>  immed23_0;
-        Bitfield<17>     mField;
-        Bitfield<8>      aField;
-        Bitfield<7>      iField;
-        Bitfield<6>      fField;
-        Bitfield<4,  0>  mode;
-
-        Bitfield<24>     aBlx;
 
         Bitfield<11, 8>  cpNum;
         Bitfield<18, 16> fn;