#define __ARCH_ARM_TYPES_HH__
#include "base/bitunion.hh"
+#include "base/hashmap.hh"
#include "base/types.hh"
namespace ArmISA
typedef uint32_t MachInst;
BitUnion64(ExtMachInst)
+ Bitfield<63, 56> newItstate;
+ // ITSTATE bits
+ Bitfield<55, 48> itstate;
+ Bitfield<55, 52> itstateCond;
+ Bitfield<51, 48> itstateMask;
+
+ // FPSCR fields
+ Bitfield<41, 40> fpscrStride;
+ Bitfield<39, 37> fpscrLen;
+
// Bitfields to select mode.
Bitfield<36> thumb;
Bitfield<35> bigThumb;
Bitfield<24, 21> htopcode8_5;
Bitfield<23> htopcode7;
Bitfield<23, 21> htopcode7_5;
+ Bitfield<22> htopcode6;
Bitfield<22, 21> htopcode6_5;
Bitfield<21, 20> htopcode5_4;
Bitfield<20> htopcode4;
MODE_MON = 22,
MODE_ABORT = 23,
MODE_UNDEFINED = 27,
- MODE_SYSTEM = 31
+ MODE_SYSTEM = 31,
+ MODE_MAXMODE = MODE_SYSTEM
};
+ static inline bool
+ badMode(OperatingMode mode)
+ {
+ switch (mode) {
+ case MODE_USER:
+ case MODE_FIQ:
+ case MODE_IRQ:
+ case MODE_SVC:
+ case MODE_MON:
+ case MODE_ABORT:
+ case MODE_UNDEFINED:
+ case MODE_SYSTEM:
+ return false;
+ default:
+ return true;
+ }
+ }
+
struct CoreSpecific {
// Empty for now on the ARM
};
} // namespace ArmISA
+namespace __hash_namespace {
+ template<>
+ struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> {
+ size_t operator()(const ArmISA::ExtMachInst &emi) const {
+ return hash<uint32_t>::operator()((uint32_t)emi);
+ };
+ };
+}
+
#endif