Mem: Reclaim some request flags used by MIPS for alignment checking.

[gem5.git] / src / arch / arm / types.hh

diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index e99a00435f5c90edb0de3e2db6aa73987912c730..3c3b29494ee72fb322f14029c9d580e480850b05 100644 (file)
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -44,6 +44,7 @@
 #define __ARCH_ARM_TYPES_HH__
 
 #include "base/bitunion.hh"
+#include "base/hashmap.hh"
 #include "base/types.hh"
 
 namespace ArmISA
@@ -51,6 +52,16 @@ namespace ArmISA
     typedef uint32_t MachInst;
 
     BitUnion64(ExtMachInst)
+        Bitfield<63, 56> newItstate;
+        // ITSTATE bits
+        Bitfield<55, 48> itstate;
+        Bitfield<55, 52> itstateCond;
+        Bitfield<51, 48> itstateMask;
+
+        // FPSCR fields
+        Bitfield<41, 40> fpscrStride;
+        Bitfield<39, 37> fpscrLen;
+
         // Bitfields to select mode.
         Bitfield<36>     thumb;
         Bitfield<35>     bigThumb;
@@ -231,13 +242,41 @@ namespace ArmISA
         MODE_MON = 22,
         MODE_ABORT = 23,
         MODE_UNDEFINED = 27,
-        MODE_SYSTEM = 31
+        MODE_SYSTEM = 31,
+        MODE_MAXMODE = MODE_SYSTEM
     };
 
+    static inline bool
+    badMode(OperatingMode mode)
+    {
+        switch (mode) {
+          case MODE_USER:
+          case MODE_FIQ:
+          case MODE_IRQ:
+          case MODE_SVC:
+          case MODE_MON:
+          case MODE_ABORT:
+          case MODE_UNDEFINED:
+          case MODE_SYSTEM:
+            return false;
+          default:
+            return true;
+        }
+    }
+
     struct CoreSpecific {
         // Empty for now on the ARM
     };
 
 } // namespace ArmISA
 
+namespace __hash_namespace {
+    template<>
+    struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> {
+        size_t operator()(const ArmISA::ExtMachInst &emi) const {
+            return hash<uint32_t>::operator()((uint32_t)emi);
+        };
+    };
+}
+
 #endif