/*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2007-2008 The Florida State University
* All rights reserved.
*
#ifndef __ARCH_ARM_TYPES_HH__
#define __ARCH_ARM_TYPES_HH__
-#include "sim/host.hh"
+#include "base/bitunion.hh"
+#include "base/types.hh"
namespace ArmISA
{
typedef uint32_t MachInst;
- typedef uint64_t ExtMachInst;
- typedef uint8_t RegIndex;
- typedef uint64_t IntReg;
+ BitUnion64(ExtMachInst)
+ // Bitfields to select mode.
+ Bitfield<36> thumb;
+ Bitfield<35> bigThumb;
+
+ // Made up bitfields that make life easier.
+ Bitfield<33> sevenAndFour;
+ Bitfield<32> isMisc;
+
+ // All the different types of opcode fields.
+ Bitfield<27, 25> encoding;
+ Bitfield<25> useImm;
+ Bitfield<24, 21> opcode;
+ Bitfield<24, 20> mediaOpcode;
+ Bitfield<24> opcode24;
+ Bitfield<23, 20> opcode23_20;
+ Bitfield<23, 21> opcode23_21;
+ Bitfield<20> opcode20;
+ Bitfield<22> opcode22;
+ Bitfield<19> opcode19;
+ Bitfield<18> opcode18;
+ Bitfield<15, 12> opcode15_12;
+ Bitfield<15> opcode15;
+ Bitfield<7, 4> miscOpcode;
+ Bitfield<7,5> opc2;
+ Bitfield<7> opcode7;
+ Bitfield<4> opcode4;
+
+ Bitfield<31, 28> condCode;
+ Bitfield<20> sField;
+ Bitfield<19, 16> rn;
+ Bitfield<15, 12> rd;
+ Bitfield<11, 7> shiftSize;
+ Bitfield<6, 5> shift;
+ Bitfield<3, 0> rm;
+
+ Bitfield<11, 8> rs;
+
+ SubBitUnion(puswl, 24, 20)
+ Bitfield<24> prepost;
+ Bitfield<23> up;
+ Bitfield<22> psruser;
+ Bitfield<21> writeback;
+ Bitfield<20> loadOp;
+ EndSubBitUnion(puswl)
+
+ Bitfield<24, 20> pubwl;
+
+ Bitfield<7, 0> imm;
+
+ Bitfield<11, 8> rotate;
+
+ Bitfield<11, 0> immed11_0;
+ Bitfield<7, 0> immed7_0;
+
+ Bitfield<11, 8> immedHi11_8;
+ Bitfield<3, 0> immedLo3_0;
+
+ Bitfield<15, 0> regList;
+
+ Bitfield<23, 0> offset;
+
+ Bitfield<23, 0> immed23_0;
+
+ Bitfield<11, 8> cpNum;
+ Bitfield<18, 16> fn;
+ Bitfield<14, 12> fd;
+ Bitfield<3> fpRegImm;
+ Bitfield<3, 0> fm;
+ Bitfield<2, 0> fpImm;
+ Bitfield<24, 20> punwl;
+
+ Bitfield<7, 0> m5Func;
+ EndBitUnion(ExtMachInst)
+
+ // Shift types for ARM instructions
+ enum ArmShiftType {
+ LSL = 0,
+ LSR,
+ ASR,
+ ROR
+ };
+
typedef uint64_t LargestRead;
// Need to use 64 bits to make sure that read requests get handled properly
- // floating point register file entry type
- typedef uint32_t FloatReg32;
- typedef uint64_t FloatReg64;
- typedef uint64_t FloatRegBits;
-
- typedef double FloatRegVal;
- typedef double FloatReg;
-
- // cop-0/cop-1 system control register
- typedef uint64_t MiscReg;
-
- typedef union {
- IntReg intreg;
- FloatReg fpreg;
- MiscReg ctrlreg;
- } AnyReg;
-
typedef int RegContextParam;
typedef int RegContextVal;
MODE_FIQ = 17,
MODE_IRQ = 18,
MODE_SVC = 19,
+ MODE_MON = 22,
MODE_ABORT = 23,
MODE_UNDEFINED = 27,
MODE_SYSTEM = 31
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