mem-cache: Add multiple eviction stats

[gem5.git] / src / arch / arm / utility.cc

diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 2f7d916d2c2bd8c025a5cbe6781c9daeb574b3bc..e3d64fadf3000c0ca91865042689be5ff0fec9cb 100644 (file)
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -192,6 +192,15 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
     dynamic_cast<TLB *>(dest->getDTBPtr())->invalidateMiscReg();
 }
 
+void
+sendEvent(ThreadContext *tc)
+{
+    if (tc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) {
+        // Post Interrupt and wake cpu if needed
+        tc->getCpuPtr()->postInterrupt(tc->threadId(), INT_SEV, 0);
+    }
+}
+
 bool
 inSecureState(ThreadContext *tc)
 {
@@ -225,9 +234,7 @@ longDescFormatInUse(ThreadContext *tc)
 RegVal
 readMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
 {
-    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
-    const ExceptionLevel current_el =
-        opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
+    const ExceptionLevel current_el = currEL(tc);
 
     const bool is_secure = isSecureBelowEL3(tc);
 
@@ -282,6 +289,41 @@ getMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
     }
 }
 
+bool
+HaveVirtHostExt(ThreadContext *tc)
+{
+    AA64MMFR1 id_aa64mmfr1 = tc->readMiscReg(MISCREG_ID_AA64MMFR1_EL1);
+    return id_aa64mmfr1.vh;
+}
+
+bool
+HaveSecureEL2Ext(ThreadContext *tc)
+{
+    AA64PFR0 id_aa64pfr0 = tc->readMiscReg(MISCREG_ID_AA64PFR0_EL1);
+    return id_aa64pfr0.sel2;
+}
+
+bool
+IsSecureEL2Enabled(ThreadContext *tc)
+{
+    SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
+    if (ArmSystem::haveEL(tc, EL2) && HaveSecureEL2Ext(tc)) {
+        if (ArmSystem::haveEL(tc, EL3))
+            return !ELIs32(tc, EL3) && scr.eel2;
+        else
+            return inSecureState(tc);
+    }
+    return false;
+}
+
+bool
+EL2Enabled(ThreadContext *tc)
+{
+    SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
+    return ArmSystem::haveEL(tc, EL2) &&
+           (!ArmSystem::haveEL(tc, EL3) || scr.ns || IsSecureEL2Enabled(tc));
+}
+
 bool
 ELIs64(ThreadContext *tc, ExceptionLevel el)
 {
@@ -300,11 +342,9 @@ ELIs32(ThreadContext *tc, ExceptionLevel el)
 bool
 ELIsInHost(ThreadContext *tc, ExceptionLevel el)
 {
-    if (!ArmSystem::haveVirtualization(tc)) {
-        return false;
-    }
-    HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
-    return (!isSecureBelowEL3(tc) && !ELIs32(tc, EL2) && hcr.e2h == 1 &&
+    const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
+    return ((IsSecureEL2Enabled(tc) || !isSecureBelowEL3(tc)) &&
+            HaveVirtHostExt(tc) && !ELIs32(tc, EL2) && hcr.e2h == 1 &&
             (el == EL2 || (el == EL0 && hcr.tge == 1)));
 }
 
@@ -341,7 +381,7 @@ ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el)
             // EL0 controlled by PSTATE
             CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
 
-            known = (cpsr.el == EL0);
+            known = (currEL(tc) == EL0);
             aarch32 = (cpsr.width == 1);
         } else {
             known = true;
@@ -356,7 +396,7 @@ ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el)
 bool
 isBigEndian64(ThreadContext *tc)
 {
-    switch (opModeToEL(currOpMode(tc))) {
+    switch (currEL(tc)) {
       case EL3:
         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).ee;
       case EL2:
@@ -820,7 +860,7 @@ decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx,
 bool
 SPAlignmentCheckEnabled(ThreadContext* tc)
 {
-    switch (opModeToEL(currOpMode(tc))) {
+    switch (currEL(tc)) {
       case EL3:
         return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).sa;
       case EL2: