#ifndef __ARCH_ARM_UTILITY_HH__
#define __ARCH_ARM_UTILITY_HH__
+#include "arch/arm/isa_traits.hh"
#include "arch/arm/miscregs.hh"
#include "arch/arm/types.hh"
-#include "base/hashmap.hh"
+#include "base/misc.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "cpu/thread_context.hh"
-namespace __hash_namespace {
- template<>
- struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> {
- size_t operator()(const ArmISA::ExtMachInst &emi) const {
- return hash<uint32_t>::operator()((uint32_t)emi);
- };
- };
-}
-
namespace ArmISA {
inline bool
tc->activate(0);
}
- template <class XC>
- Fault
- checkFpEnableFault(XC *xc)
+ static inline bool
+ isThumb(Addr pc)
{
- return NoFault;
+ return (pc & PcTBit);
}
static inline void
vfpEnabled(CPACR cpacr, CPSR cpsr)
{
return cpacr.cp10 == 0x3 ||
- (cpacr.cp10 == 0x2 && inPrivilegedMode(cpsr));
+ (cpacr.cp10 == 0x1 && inPrivilegedMode(cpsr));
}
static inline bool
return !cpacr.asedis && vfpEnabled(cpacr, cpsr, fpexc);
}
-uint64_t getArgument(ThreadContext *tc, int number, bool fp);
+uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
Fault setCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2);
Fault readCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2);
+void skipFunction(ThreadContext *tc);
+
};