Mem: Reclaim some request flags used by MIPS for alignment checking.

[gem5.git] / src / arch / arm / utility.hh

diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 43e7b14ab04faa175b390d322230ce63113d8bc5..571a74ef8b55b861899ea4979e6f44669b2cafde 100644 (file)
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  * Copyright (c) 2007-2008 The Florida State University
  * All rights reserved.
@@ -33,21 +45,14 @@
 #ifndef __ARCH_ARM_UTILITY_HH__
 #define __ARCH_ARM_UTILITY_HH__
 
+#include "arch/arm/isa_traits.hh"
 #include "arch/arm/miscregs.hh"
 #include "arch/arm/types.hh"
-#include "base/hashmap.hh"
+#include "base/misc.hh"
+#include "base/trace.hh"
 #include "base/types.hh"
 #include "cpu/thread_context.hh"
 
-namespace __hash_namespace {
-    template<>
-    struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> {
-        size_t operator()(const ArmISA::ExtMachInst &emi) const {
-            return hash<uint32_t>::operator()((uint32_t)emi);
-        };
-    };
-}
-
 namespace ArmISA {
 
     inline bool
@@ -70,7 +75,7 @@ namespace ArmISA {
             case COND_GT: return !(cpsr.n ^ cpsr.v || cpsr.z);
             case COND_LE: return  (cpsr.n ^ cpsr.v || cpsr.z);
             case COND_AL: return true;
-            case COND_NV: return false;
+            case COND_UC: return true;
             default:
                 panic("Unhandled predicate condition: %d\n", code);
         }
@@ -83,35 +88,15 @@ namespace ArmISA {
     template <class TC>
     void zeroRegisters(TC *tc);
 
-    // Instruction address compression hooks
-    static inline Addr realPCToFetchPC(const Addr &addr) {
-        return addr;
-    }
-
-    static inline Addr fetchPCToRealPC(const Addr &addr) {
-        return addr;
-    }
-
-    // the size of "fetched" instructions
-    static inline size_t fetchInstSize() {
-        return sizeof(MachInst);
-    }
-
-    static inline MachInst makeRegisterCopy(int dest, int src) {
-        panic("makeRegisterCopy not implemented");
-        return 0;
-    }
-
     inline void startupCPU(ThreadContext *tc, int cpuId)
     {
         tc->activate(0);
     }
 
-    template <class XC>
-    Fault
-    checkFpEnableFault(XC *xc)
+    static inline bool
+    isThumb(Addr pc)
     {
-        return NoFault;
+        return (pc & PcTBit);
     }
 
     static inline void
@@ -128,13 +113,55 @@ namespace ArmISA {
 
     void initCPU(ThreadContext *tc, int cpuId);
     
+    static inline bool
+    inUserMode(CPSR cpsr)
+    {
+        return cpsr.mode == MODE_USER;
+    }
+
     static inline bool
     inUserMode(ThreadContext *tc)
     {
-        return (tc->readMiscRegNoEffect(MISCREG_CPSR) & 0x1f) == MODE_USER;
+        return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR));
+    }
+
+    static inline bool
+    inPrivilegedMode(CPSR cpsr)
+    {
+        return !inUserMode(cpsr);
+    }
+
+    static inline bool
+    inPrivilegedMode(ThreadContext *tc)
+    {
+        return !inUserMode(tc);
     }
 
-uint64_t getArgument(ThreadContext *tc, int number, bool fp);
+    static inline bool
+    vfpEnabled(CPACR cpacr, CPSR cpsr)
+    {
+        return cpacr.cp10 == 0x3 ||
+            (cpacr.cp10 == 0x1 && inPrivilegedMode(cpsr));
+    }
+
+    static inline bool
+    vfpEnabled(CPACR cpacr, CPSR cpsr, FPEXC fpexc)
+    {
+        return fpexc.en && vfpEnabled(cpacr, cpsr);
+    }
+
+    static inline bool
+    neonEnabled(CPACR cpacr, CPSR cpsr, FPEXC fpexc)
+    {
+        return !cpacr.asedis && vfpEnabled(cpacr, cpsr, fpexc);
+    }
+
+uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
+    
+Fault setCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2);
+Fault readCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2);
+
+void skipFunction(ThreadContext *tc);
 
 };