#ifndef __ARCH_ARM_UTILITY_HH__
#define __ARCH_ARM_UTILITY_HH__
+#include "arch/arm/isa_traits.hh"
#include "arch/arm/miscregs.hh"
#include "arch/arm/types.hh"
-#include "base/hashmap.hh"
+#include "base/misc.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "cpu/thread_context.hh"
-namespace __hash_namespace {
- template<>
- struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> {
- size_t operator()(const ArmISA::ExtMachInst &emi) const {
- return hash<uint32_t>::operator()((uint32_t)emi);
- };
- };
-}
-
namespace ArmISA {
inline bool
template <class TC>
void zeroRegisters(TC *tc);
- // Instruction address compression hooks
- static inline Addr realPCToFetchPC(const Addr &addr) {
- return addr;
- }
-
- static inline Addr fetchPCToRealPC(const Addr &addr) {
- return addr;
- }
-
- // the size of "fetched" instructions
- static inline size_t fetchInstSize() {
- return sizeof(MachInst);
- }
-
- static inline MachInst makeRegisterCopy(int dest, int src) {
- panic("makeRegisterCopy not implemented");
- return 0;
- }
-
inline void startupCPU(ThreadContext *tc, int cpuId)
{
tc->activate(0);
}
- template <class XC>
- Fault
- checkFpEnableFault(XC *xc)
+ static inline bool
+ isThumb(Addr pc)
{
- return NoFault;
+ return (pc & PcTBit);
}
static inline void
void initCPU(ThreadContext *tc, int cpuId);
+ static inline bool
+ inUserMode(CPSR cpsr)
+ {
+ return cpsr.mode == MODE_USER;
+ }
+
static inline bool
inUserMode(ThreadContext *tc)
{
- return (tc->readMiscRegNoEffect(MISCREG_CPSR) & 0x1f) == MODE_USER;
+ return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR));
}
- static inline std::string
- inst2string(MachInst machInst)
+ static inline bool
+ inPrivilegedMode(CPSR cpsr)
{
- std::string str = "";
- uint32_t mask = (1 << 31);
+ return !inUserMode(cpsr);
+ }
- while (mask) {
- str += ((machInst & mask) ? "1" : "0");
- mask = mask >> 1;
- }
+ static inline bool
+ inPrivilegedMode(ThreadContext *tc)
+ {
+ return !inUserMode(tc);
+ }
- return str;
+ static inline bool
+ vfpEnabled(CPACR cpacr, CPSR cpsr)
+ {
+ return cpacr.cp10 == 0x3 ||
+ (cpacr.cp10 == 0x1 && inPrivilegedMode(cpsr));
}
-uint64_t getArgument(ThreadContext *tc, int number, bool fp);
+ static inline bool
+ vfpEnabled(CPACR cpacr, CPSR cpsr, FPEXC fpexc)
+ {
+ return fpexc.en && vfpEnabled(cpacr, cpsr);
+ }
+
+ static inline bool
+ neonEnabled(CPACR cpacr, CPSR cpsr, FPEXC fpexc)
+ {
+ return !cpacr.asedis && vfpEnabled(cpacr, cpsr, fpexc);
+ }
+
+uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
Fault setCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2);
Fault readCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2);
+void skipFunction(ThreadContext *tc);
+
};