ARM: Fix the "open" flag constants.

[gem5.git] / src / arch / isa_parser.py

diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index 8facd5cce67989003e45c76a2fc239c688bf19ae..6f002c05ba196c950945d77d42d560eb4fee85b6 100755 (executable)
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -1173,10 +1173,9 @@ def buildOperandTypeMap(userDict, lineno):
 # (e.g., "32-bit integer register").
 #
 class Operand(object):
-    def buildReadCode(self, func = None, width = None):
+    def buildReadCode(self, func = None):
         code = self.read_code % {"name": self.base_name,
                                  "func": func,
-                                 "width": width,
                                  "op_idx": self.src_reg_idx,
                                  "reg_idx": self.reg_spec,
                                  "size": self.size,
@@ -1188,14 +1187,13 @@ class Operand(object):
             return '%s = %s;\n' % \
                    (self.base_name, code)
 
-    def buildWriteCode(self, func = None, width = None):
+    def buildWriteCode(self, func = None):
         if (self.size != self.dflt_size and self.is_signed):
             final_val = 'sext<%d>(%s)' % (self.size, self.base_name)
         else:
             final_val = self.base_name
         code = self.write_code % {"name": self.base_name,
                                   "func": func,
-                                  "width": width,
                                   "op_idx": self.dest_reg_idx,
                                   "reg_idx": self.reg_spec,
                                   "size": self.size,
@@ -1269,9 +1267,6 @@ class Operand(object):
     def isControlReg(self):
         return 0
 
-    def isIControlReg(self):
-        return 0
-
     def getFlags(self):
         # note the empty slice '[:]' gives us a copy of self.flags[0]
         # instead of a reference to it
@@ -1358,29 +1353,15 @@ class FloatRegOperand(Operand):
 
     def makeRead(self):
         bit_select = 0
-        width = 0;
-        if (self.ctype == 'float'):
-            func = 'readFloatRegOperand'
-            width = 32;
-        elif (self.ctype == 'double'):
+        if (self.ctype == 'float' or self.ctype == 'double'):
             func = 'readFloatRegOperand'
-            width = 64;
         else:
             func = 'readFloatRegOperandBits'
-            if (self.ctype == 'uint32_t'):
-                width = 32;
-            elif (self.ctype == 'uint64_t'):
-                width = 64;
             if (self.size != self.dflt_size):
                 bit_select = 1
-        if width:
-            base = 'xc->%s(this, %d, %d)' % \
-                   (func, self.src_reg_idx, width)
-        else:
-            base = 'xc->%s(this, %d)' % \
-                   (func, self.src_reg_idx)
+        base = 'xc->%s(this, %d)' % (func, self.src_reg_idx)
         if self.read_code != None:
-            return self.buildReadCode(func, width)
+            return self.buildReadCode(func)
         if bit_select:
             return '%s = bits(%s, %d, 0);\n' % \
                    (self.base_name, base, self.size-1)
@@ -1390,36 +1371,23 @@ class FloatRegOperand(Operand):
     def makeWrite(self):
         final_val = self.base_name
         final_ctype = self.ctype
-        widthSpecifier = ''
-        width = 0
-        if (self.ctype == 'float'):
-            width = 32
-            func = 'setFloatRegOperand'
-        elif (self.ctype == 'double'):
-            width = 64
+        if (self.ctype == 'float' or self.ctype == 'double'):
             func = 'setFloatRegOperand'
-        elif (self.ctype == 'uint32_t'):
-            func = 'setFloatRegOperandBits'
-            width = 32
-        elif (self.ctype == 'uint64_t'):
+        elif (self.ctype == 'uint32_t' or self.ctype == 'uint64_t'):
             func = 'setFloatRegOperandBits'
-            width = 64
         else:
             func = 'setFloatRegOperandBits'
             final_ctype = 'uint%d_t' % self.dflt_size
             if (self.size != self.dflt_size and self.is_signed):
                 final_val = 'sext<%d>(%s)' % (self.size, self.base_name)
         if self.write_code != None:
-            return self.buildWriteCode(func, width)
-        if width:
-            widthSpecifier = ', %d' % width
+            return self.buildWriteCode(func)
         wb = '''
         {
             %s final_val = %s;
-            xc->%s(this, %d, final_val%s);\n
+            xc->%s(this, %d, final_val);\n
             if (traceData) { traceData->setData(final_val); }
-        }''' % (final_ctype, final_val, func, self.dest_reg_idx,
-                widthSpecifier)
+        }''' % (final_ctype, final_val, func, self.dest_reg_idx)
         return wb
 
 class ControlRegOperand(Operand):
@@ -1463,47 +1431,6 @@ class ControlRegOperand(Operand):
               self.base_name
         return wb
 
-class IControlRegOperand(Operand):
-    def isReg(self):
-        return 1
-
-    def isIControlReg(self):
-        return 1
-
-    def makeConstructor(self):
-        c = ''
-        if self.is_src:
-            c += '\n\t_srcRegIdx[%d] = %s + Ctrl_Base_DepTag;' % \
-                 (self.src_reg_idx, self.reg_spec)
-        if self.is_dest:
-            c += '\n\t_destRegIdx[%d] = %s + Ctrl_Base_DepTag;' % \
-                 (self.dest_reg_idx, self.reg_spec)
-        return c
-
-    def makeRead(self):
-        bit_select = 0
-        if (self.ctype == 'float' or self.ctype == 'double'):
-            error(0, 'Attempt to read control register as FP')
-        if self.read_code != None:
-            return self.buildReadCode('readMiscReg')
-        base = 'xc->readMiscReg(%s)' % self.reg_spec
-        if self.size == self.dflt_size:
-            return '%s = %s;\n' % (self.base_name, base)
-        else:
-            return '%s = bits(%s, %d, 0);\n' % \
-                   (self.base_name, base, self.size-1)
-
-    def makeWrite(self):
-        if (self.ctype == 'float' or self.ctype == 'double'):
-            error(0, 'Attempt to write control register as FP')
-        if self.write_code != None:
-            return self.buildWriteCode('setMiscReg')
-        wb = 'xc->setMiscReg(%s, %s);\n' % \
-             (self.reg_spec, self.base_name)
-        wb += 'if (traceData) { traceData->setData(%s); }' % \
-              self.base_name
-        return wb
-
 class ControlBitfieldOperand(ControlRegOperand):
     def makeRead(self):
         bit_select = 0