if operands.readPC or operands.setPC:
myDict['op_decl'] += 'TheISA::PCState __parserAutoPCState;\n'
+ # In case there are predicated register reads and write, declare
+ # the variables for register indicies. It is being assumed that
+ # all the operands in the OperandList are also in the
+ # SubOperandList and in the same order. Otherwise, it is
+ # expected that predication would not be used for the operands.
+ if operands.predRead:
+ myDict['op_decl'] += 'uint8_t _sourceIndex = 0;\n'
+ if operands.predWrite:
+ myDict['op_decl'] += 'uint8_t M5_VAR_USED _destIndex = 0;\n'
+
is_src = lambda op: op.is_src
is_dest = lambda op: op.is_dest
op_wb_str = op_desc.op_wb + op_wb_str
myDict['op_wb'] = op_wb_str
- if d.operands.memOperand:
- myDict['mem_acc_type'] = d.operands.memOperand.mem_acc_type
-
elif isinstance(d, dict):
# if the argument is a dictionary, we just use it.
myDict.update(d)
if hasattr(self, 'eff_ext'):
self.ctype = parser.operandTypeMap[self.eff_ext]
- # note that mem_acc_type is undefined for non-mem operands...
- # template must be careful not to use it if it doesn't apply.
- if self.isMem():
- self.mem_acc_type = self.ctype
-
# Finalize additional fields (primarily code fields). This step
# is done separately since some of these fields may depend on the
# register index enumeration that hasn't been performed yet at the
- # time of __init__().
- def finalize(self):
+ # time of __init__(). The register index enumeration is affected
+ # by predicated register reads/writes. Hence, we forward the flags
+ # that indicate whether or not predication is in use.
+ def finalize(self, predRead, predWrite):
self.flags = self.getFlags()
- self.constructor = self.makeConstructor()
+ self.constructor = self.makeConstructor(predRead, predWrite)
self.op_decl = self.makeDecl()
if self.is_src:
- self.op_rd = self.makeRead()
+ self.op_rd = self.makeRead(predRead)
self.op_src_decl = self.makeDecl()
else:
self.op_rd = ''
self.op_src_decl = ''
if self.is_dest:
- self.op_wb = self.makeWrite()
+ self.op_wb = self.makeWrite(predWrite)
self.op_dest_decl = self.makeDecl()
else:
self.op_wb = ''
def isPCPart(self):
return self.isPCState() and self.reg_spec
+ def hasReadPred(self):
+ return self.read_predicate != None
+
+ def hasWritePred(self):
+ return self.write_predicate != None
+
def getFlags(self):
# note the empty slice '[:]' gives us a copy of self.flags[0]
# instead of a reference to it
def isIntReg(self):
return 1
- def makeConstructor(self):
- c = ''
+ def makeConstructor(self, predRead, predWrite):
+ c_src = ''
+ c_dest = ''
+
if self.is_src:
- c += '\n\t_srcRegIdx[%d] = %s;' % \
- (self.src_reg_idx, self.reg_spec)
+ c_src = '\n\t_srcRegIdx[_numSrcRegs++] = %s;' % (self.reg_spec)
+ if self.hasReadPred():
+ c_src = '\n\tif (%s) {%s\n\t}' % \
+ (self.read_predicate, c_src)
+
if self.is_dest:
- c += '\n\t_destRegIdx[%d] = %s;' % \
- (self.dest_reg_idx, self.reg_spec)
- return c
+ c_dest = '\n\t_destRegIdx[_numDestRegs++] = %s;' % \
+ (self.reg_spec)
+ c_dest += '\n\t_numIntDestRegs++;'
+ if self.hasWritePred():
+ c_dest = '\n\tif (%s) {%s\n\t}' % \
+ (self.write_predicate, c_dest)
- def makeRead(self):
+ return c_src + c_dest
+
+ def makeRead(self, predRead):
if (self.ctype == 'float' or self.ctype == 'double'):
error('Attempt to read integer register as FP')
if self.read_code != None:
return self.buildReadCode('readIntRegOperand')
- int_reg_val = 'xc->readIntRegOperand(this, %d)' % self.src_reg_idx
+
+ int_reg_val = ''
+ if predRead:
+ int_reg_val = 'xc->readIntRegOperand(this, _sourceIndex++)'
+ if self.hasReadPred():
+ int_reg_val = '(%s) ? %s : 0' % \
+ (self.read_predicate, int_reg_val)
+ else:
+ int_reg_val = 'xc->readIntRegOperand(this, %d)' % self.src_reg_idx
+
return '%s = %s;\n' % (self.base_name, int_reg_val)
- def makeWrite(self):
+ def makeWrite(self, predWrite):
if (self.ctype == 'float' or self.ctype == 'double'):
error('Attempt to write integer register as FP')
if self.write_code != None:
return self.buildWriteCode('setIntRegOperand')
+
+ if predWrite:
+ wp = 'true'
+ if self.hasWritePred():
+ wp = self.write_predicate
+
+ wcond = 'if (%s)' % (wp)
+ windex = '_destIndex++'
+ else:
+ wcond = ''
+ windex = '%d' % self.dest_reg_idx
+
wb = '''
+ %s
{
%s final_val = %s;
- xc->setIntRegOperand(this, %d, final_val);\n
+ xc->setIntRegOperand(this, %s, final_val);\n
if (traceData) { traceData->setData(final_val); }
- }''' % (self.ctype, self.base_name, self.dest_reg_idx)
+ }''' % (wcond, self.ctype, self.base_name, windex)
+
return wb
class FloatRegOperand(Operand):
def isFloatReg(self):
return 1
- def makeConstructor(self):
- c = ''
+ def makeConstructor(self, predRead, predWrite):
+ c_src = ''
+ c_dest = ''
+
if self.is_src:
- c += '\n\t_srcRegIdx[%d] = %s + FP_Base_DepTag;' % \
- (self.src_reg_idx, self.reg_spec)
+ c_src = '\n\t_srcRegIdx[_numSrcRegs++] = %s + FP_Base_DepTag;' % \
+ (self.reg_spec)
+
if self.is_dest:
- c += '\n\t_destRegIdx[%d] = %s + FP_Base_DepTag;' % \
- (self.dest_reg_idx, self.reg_spec)
- return c
+ c_dest = \
+ '\n\t_destRegIdx[_numDestRegs++] = %s + FP_Base_DepTag;' % \
+ (self.reg_spec)
+ c_dest += '\n\t_numFPDestRegs++;'
- def makeRead(self):
+ return c_src + c_dest
+
+ def makeRead(self, predRead):
bit_select = 0
if (self.ctype == 'float' or self.ctype == 'double'):
func = 'readFloatRegOperand'
func = 'readFloatRegOperandBits'
if self.read_code != None:
return self.buildReadCode(func)
- return '%s = xc->%s(this, %d);\n' % \
- (self.base_name, func, self.src_reg_idx)
- def makeWrite(self):
+ if predRead:
+ rindex = '_sourceIndex++'
+ else:
+ rindex = '%d' % self.src_reg_idx
+
+ return '%s = xc->%s(this, %s);\n' % \
+ (self.base_name, func, rindex)
+
+ def makeWrite(self, predWrite):
if (self.ctype == 'float' or self.ctype == 'double'):
func = 'setFloatRegOperand'
else:
func = 'setFloatRegOperandBits'
if self.write_code != None:
return self.buildWriteCode(func)
+
+ if predWrite:
+ wp = '_destIndex++'
+ else:
+ wp = '%d' % self.dest_reg_idx
+ wp = 'xc->%s(this, %s, final_val);' % (func, wp)
+
wb = '''
{
%s final_val = %s;
- xc->%s(this, %d, final_val);\n
+ %s\n
if (traceData) { traceData->setData(final_val); }
- }''' % (self.ctype, self.base_name, func, self.dest_reg_idx)
+ }''' % (self.ctype, self.base_name, wp)
return wb
class ControlRegOperand(Operand):
def isControlReg(self):
return 1
- def makeConstructor(self):
- c = ''
+ def makeConstructor(self, predRead, predWrite):
+ c_src = ''
+ c_dest = ''
+
if self.is_src:
- c += '\n\t_srcRegIdx[%d] = %s + Ctrl_Base_DepTag;' % \
- (self.src_reg_idx, self.reg_spec)
+ c_src = \
+ '\n\t_srcRegIdx[_numSrcRegs++] = %s + Ctrl_Base_DepTag;' % \
+ (self.reg_spec)
+
if self.is_dest:
- c += '\n\t_destRegIdx[%d] = %s + Ctrl_Base_DepTag;' % \
- (self.dest_reg_idx, self.reg_spec)
- return c
+ c_dest = \
+ '\n\t_destRegIdx[_numDestRegs++] = %s + Ctrl_Base_DepTag;' % \
+ (self.reg_spec)
+
+ return c_src + c_dest
- def makeRead(self):
+ def makeRead(self, predRead):
bit_select = 0
if (self.ctype == 'float' or self.ctype == 'double'):
error('Attempt to read control register as FP')
if self.read_code != None:
return self.buildReadCode('readMiscRegOperand')
+
+ if predRead:
+ rindex = '_sourceIndex++'
+ else:
+ rindex = '%d' % self.src_reg_idx
+
return '%s = xc->readMiscRegOperand(this, %s);\n' % \
- (self.base_name, self.src_reg_idx)
+ (self.base_name, rindex)
- def makeWrite(self):
+ def makeWrite(self, predWrite):
if (self.ctype == 'float' or self.ctype == 'double'):
error('Attempt to write control register as FP')
if self.write_code != None:
return self.buildWriteCode('setMiscRegOperand')
+
+ if predWrite:
+ windex = '_destIndex++'
+ else:
+ windex = '%d' % self.dest_reg_idx
+
wb = 'xc->setMiscRegOperand(this, %s, %s);\n' % \
- (self.dest_reg_idx, self.base_name)
+ (windex, self.base_name)
wb += 'if (traceData) { traceData->setData(%s); }' % \
self.base_name
+
return wb
class MemOperand(Operand):
def isMem(self):
return 1
- def makeConstructor(self):
+ def makeConstructor(self, predRead, predWrite):
return ''
def makeDecl(self):
# Declare memory data variable.
return '%s %s = 0;\n' % (self.ctype, self.base_name)
- def makeRead(self):
+ def makeRead(self, predRead):
if self.read_code != None:
return self.buildReadCode()
return ''
- def makeWrite(self):
+ def makeWrite(self, predWrite):
if self.write_code != None:
return self.buildWriteCode()
return ''
class PCStateOperand(Operand):
- def makeConstructor(self):
+ def makeConstructor(self, predRead, predWrite):
return ''
- def makeRead(self):
+ def makeRead(self, predRead):
if self.reg_spec:
# A component of the PC state.
return '%s = __parserAutoPCState.%s();\n' % \
# The whole PC state itself.
return '%s = xc->pcState();\n' % self.base_name
- def makeWrite(self):
+ def makeWrite(self, predWrite):
if self.reg_spec:
# A component of the PC state.
return '__parserAutoPCState.%s(%s);\n' % \
def __init__(self, parser, code):
self.items = []
self.bases = {}
- # delete comments so we don't match on reg specifiers inside
- code = commentRE.sub('', code)
+ # delete strings and comments so we don't match on operands inside
+ for regEx in (stringRE, commentRE):
+ code = regEx.sub('', code)
# search for operands
next_pos = 0
while 1:
self.numDestRegs = 0
self.numFPDestRegs = 0
self.numIntDestRegs = 0
+ self.numMiscDestRegs = 0
self.memOperand = None
+
+ # Flags to keep track if one or more operands are to be read/written
+ # conditionally.
+ self.predRead = False
+ self.predWrite = False
+
for op_desc in self.items:
if op_desc.isReg():
if op_desc.is_src:
self.numFPDestRegs += 1
elif op_desc.isIntReg():
self.numIntDestRegs += 1
+ elif op_desc.isControlReg():
+ self.numMiscDestRegs += 1
elif op_desc.isMem():
if self.memOperand:
error("Code block has more than one memory operand.")
self.memOperand = op_desc
+
+ # Check if this operand has read/write predication. If true, then
+ # the microop will dynamically index source/dest registers.
+ self.predRead = self.predRead or op_desc.hasReadPred()
+ self.predWrite = self.predWrite or op_desc.hasWritePred()
+
if parser.maxInstSrcRegs < self.numSrcRegs:
parser.maxInstSrcRegs = self.numSrcRegs
if parser.maxInstDestRegs < self.numDestRegs:
parser.maxInstDestRegs = self.numDestRegs
+ if parser.maxMiscDestRegs < self.numMiscDestRegs:
+ parser.maxMiscDestRegs = self.numMiscDestRegs
+
# now make a final pass to finalize op_desc fields that may depend
# on the register enumeration
for op_desc in self.items:
- op_desc.finalize()
+ op_desc.finalize(self.predRead, self.predWrite)
def __len__(self):
return len(self.items)
def __init__(self, parser, code, master_list):
self.items = []
self.bases = {}
- # delete comments so we don't match on reg specifiers inside
- code = commentRE.sub('', code)
+ # delete strings and comments so we don't match on operands inside
+ for regEx in (stringRE, commentRE):
+ code = regEx.sub('', code)
# search for operands
next_pos = 0
while 1:
# Whether this instruction manipulates the whole PC or parts of it.
# Mixing the two is a bad idea and flagged as an error.
self.pcPart = None
+
+ # Flags to keep track if one or more operands are to be read/written
+ # conditionally.
+ self.predRead = False
+ self.predWrite = False
+
for op_desc in self.items:
if op_desc.isPCPart():
self.readPC = True
if op_desc.is_dest:
self.setPC = True
+
if op_desc.isPCState():
if self.pcPart is not None:
if self.pcPart and not op_desc.isPCPart() or \
not self.pcPart and op_desc.isPCPart():
error("Mixed whole and partial PC state operands.")
self.pcPart = op_desc.isPCPart()
+
if op_desc.isMem():
if self.memOperand:
error("Code block has more than one memory operand.")
self.memOperand = op_desc
+ # Check if this operand has read/write predication. If true, then
+ # the microop will dynamically index source/dest registers.
+ self.predRead = self.predRead or op_desc.hasReadPred()
+ self.predWrite = self.predWrite or op_desc.hasWritePred()
+
+# Regular expression object to match C++ strings
+stringRE = re.compile(r'"([^"\\]|\\.)*"')
+
# Regular expression object to match C++ comments
# (used in findOperands())
-commentRE = re.compile(r'//.*\n')
+commentRE = re.compile(r'(^)?[^\S\n]*/(?:\*(.*?)\*/[^\S\n]*|/[^\n]*)($)?',
+ re.DOTALL | re.MULTILINE)
# Regular expression object to match assignment statements
# (used in findOperands())
self.snippets = snippets
self.operands = OperandList(parser, compositeCode)
- self.constructor = self.operands.concatAttrStrings('constructor')
- self.constructor += \
- '\n\t_numSrcRegs = %d;' % self.operands.numSrcRegs
- self.constructor += \
- '\n\t_numDestRegs = %d;' % self.operands.numDestRegs
- self.constructor += \
- '\n\t_numFPDestRegs = %d;' % self.operands.numFPDestRegs
- self.constructor += \
- '\n\t_numIntDestRegs = %d;' % self.operands.numIntDestRegs
+
+ # The header of the constructor declares the variables to be used
+ # in the body of the constructor.
+ header = ''
+ header += '\n\t_numSrcRegs = 0;'
+ header += '\n\t_numDestRegs = 0;'
+ header += '\n\t_numFPDestRegs = 0;'
+ header += '\n\t_numIntDestRegs = 0;'
+
+ self.constructor = header + \
+ self.operands.concatAttrStrings('constructor')
+
self.flags = self.operands.concatAttrLists('flags')
# Make a basic guess on the operand class (function unit type).
const int MaxInstSrcRegs = %(MaxInstSrcRegs)d;
const int MaxInstDestRegs = %(MaxInstDestRegs)d;
+ const int MaxMiscDestRegs = %(MaxMiscDestRegs)d;
} // namespace %(namespace)s
self.maxInstSrcRegs = 0
self.maxInstDestRegs = 0
+ self.maxMiscDestRegs = 0
#####################################################################
#
# wrap the decode block as a function definition
t[4].wrap_decode_block('''
StaticInstPtr
-%(isa_name)s::decodeInst(%(isa_name)s::ExtMachInst machInst)
+%(isa_name)s::Decoder::decodeInst(%(isa_name)s::ExtMachInst machInst)
{
using namespace %(namespace)s;
''' % vars(), '}')
def buildOperandNameMap(self, user_dict, lineno):
operand_name = {}
for op_name, val in user_dict.iteritems():
- base_cls_name, dflt_ext, reg_spec, flags, sort_pri = val[:5]
- if len(val) > 5:
- read_code = val[5]
- else:
- read_code = None
- if len(val) > 6:
- write_code = val[6]
- else:
- write_code = None
- if len(val) > 7:
- error(lineno,
- 'error: too many attributes for operand "%s"' %
+
+ # Check if extra attributes have been specified.
+ if len(val) > 9:
+ error(lineno, 'error: too many attributes for operand "%s"' %
base_cls_name)
+ # Pad val with None in case optional args are missing
+ val += (None, None, None, None)
+ base_cls_name, dflt_ext, reg_spec, flags, sort_pri, \
+ read_code, write_code, read_predicate, write_predicate = val[:9]
+
# Canonical flag structure is a triple of lists, where each list
# indicates the set of flags implied by this operand always, when
# used as a source, and when used as a dest, respectively.
(uncond_flags, src_flags, dest_flags) = flags
flags = (makeList(uncond_flags),
makeList(src_flags), makeList(dest_flags))
+
# Accumulate attributes of new operand class in tmp_dict
tmp_dict = {}
attrList = ['reg_spec', 'flags', 'sort_pri',
- 'read_code', 'write_code']
+ 'read_code', 'write_code',
+ 'read_predicate', 'write_predicate']
if dflt_ext:
dflt_ctype = self.operandTypeMap[dflt_ext]
attrList.extend(['dflt_ctype', 'dflt_ext'])
for attr in attrList:
tmp_dict[attr] = eval(attr)
tmp_dict['base_name'] = op_name
+
# New class name will be e.g. "IntReg_Ra"
cls_name = base_cls_name + '_' + op_name
# Evaluate string arg to get class object. Note that the
# Define operand variables.
operands = user_dict.keys()
+ extensions = self.operandTypeMap.keys()
- operandsREString = (r'''
- (?<![\w\.]) # neg. lookbehind assertion: prevent partial matches
- ((%s)(?:\.(\w+))?) # match: operand with optional '.' then suffix
- (?![\w\.]) # neg. lookahead assertion: prevent partial matches
- '''
- % string.join(operands, '|'))
+ operandsREString = r'''
+ (?<!\w) # neg. lookbehind assertion: prevent partial matches
+ ((%s)(?:_(%s))?) # match: operand with optional '_' then suffix
+ (?!\w) # neg. lookahead assertion: prevent partial matches
+ ''' % (string.join(operands, '|'), string.join(extensions, '|'))
self.operandsRE = re.compile(operandsREString, re.MULTILINE|re.VERBOSE)
# Same as operandsREString, but extension is mandatory, and only two
# groups are returned (base and ext, not full name as above).
# Used for subtituting '_' for '.' to make C++ identifiers.
- operandsWithExtREString = (r'(?<![\w\.])(%s)\.(\w+)(?![\w\.])'
- % string.join(operands, '|'))
+ operandsWithExtREString = r'(?<!\w)(%s)_(%s)(?!\w)' \
+ % (string.join(operands, '|'), string.join(extensions, '|'))
self.operandsWithExtRE = \
re.compile(operandsWithExtREString, re.MULTILINE)
# value of the globals.
MaxInstSrcRegs = self.maxInstSrcRegs
MaxInstDestRegs = self.maxInstDestRegs
+ MaxMiscDestRegs = self.maxMiscDestRegs
# max_inst_regs.hh
self.update_if_needed('max_inst_regs.hh',
max_inst_regs_template % vars())