ARM: Don't downconvert ExtMachInsts to MachInsts.

[gem5.git] / src / arch / isa_parser.py

diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index ef21f7ceb1799dfe6851b8cd7a4b303fd756fb59..fcb7ea7e43d8ea20ed75d53b1c16403ab86982c5 100755 (executable)
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -25,7 +25,6 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
 # Authors: Steve Reinhardt
-#          Korey Sewell
 
 import os
 import sys
@@ -116,7 +115,7 @@ t_SEMI             = r';'
 t_DOT              = r'\.'
 t_COLON            = r':'
 t_DBLCOLON         = r'::'
-t_ASTERISK        = r'\*'
+t_ASTERISK         = r'\*'
 
 # Identifiers and reserved words
 reserved_map = { }
@@ -480,7 +479,7 @@ def p_excess_args_param(t):
 
 #
 # A decode block looks like:
-#      decode <field1> [, <field2>]* [default <inst>] { ... }
+#       decode <field1> [, <field2>]* [default <inst>] { ... }
 #
 def p_decode_block(t):
     'decode_block : DECODE ID opt_default LBRACE decode_stmt_list RBRACE'
@@ -1149,7 +1148,7 @@ def buildOperandTypeMap(userDict, lineno):
             ctype = 'uint%d_t' % size
             is_signed = 0
         elif desc == 'float':
-            is_signed = 1      # shouldn't really matter
+            is_signed = 1       # shouldn't really matter
             if size == 32:
                 ctype = 'float'
             elif size == 64:
@@ -1235,6 +1234,9 @@ class Operand(object):
     def isControlReg(self):
         return 0
 
+    def isIControlReg(self):
+        return 0
+
     def getFlags(self):
         # note the empty slice '[:]' gives us a copy of self.flags[0]
         # instead of a reference to it
@@ -1592,9 +1594,9 @@ def buildOperandNameMap(userDict, lineno):
     operands = userDict.keys()
 
     operandsREString = (r'''
-    (?<![\w\.])             # neg. lookbehind assertion: prevent partial matches
+    (?<![\w\.])      # neg. lookbehind assertion: prevent partial matches
     ((%s)(?:\.(\w+))?)   # match: operand with optional '.' then suffix
-    (?![\w\.])      # neg. lookahead assertion: prevent partial matches
+    (?![\w\.])       # neg. lookahead assertion: prevent partial matches
     '''
                         % string.join(operands, '|'))
 
@@ -1610,6 +1612,8 @@ def buildOperandNameMap(userDict, lineno):
     global operandsWithExtRE
     operandsWithExtRE = re.compile(operandsWithExtREString, re.MULTILINE)
 
+maxInstSrcRegs = 0
+maxInstDestRegs = 0
 
 class OperandList:
 
@@ -1673,6 +1677,12 @@ class OperandList:
                 if self.memOperand:
                     error(0, "Code block has more than one memory operand.")
                 self.memOperand = op_desc
+        global maxInstSrcRegs
+        global maxInstDestRegs
+        if maxInstSrcRegs < self.numSrcRegs:
+            maxInstSrcRegs = self.numSrcRegs
+        if maxInstDestRegs < self.numDestRegs:
+            maxInstDestRegs = self.numDestRegs
         # now make a final pass to finalize op_desc fields that may depend
         # on the register enumeration
         for op_desc in self.items:
@@ -1892,6 +1902,22 @@ namespace %(namespace)s {
 %(decode_function)s
 '''
 
+max_inst_regs_template = '''
+/*
+ * DO NOT EDIT THIS FILE!!!
+ *
+ * It was automatically generated from the ISA description in %(filename)s
+ */
+
+namespace %(namespace)s {
+
+    const int MaxInstSrcRegs = %(MaxInstSrcRegs)d;
+    const int MaxInstDestRegs = %(MaxInstDestRegs)d;
+
+} // namespace %(namespace)s
+
+'''
+
 
 # Update the output file only if the new contents are different from
 # the current contents.  Minimizes the files that need to be rebuilt
@@ -1991,6 +2017,16 @@ def parse_isa_desc(isa_desc_file, output_dir):
         update_if_needed(output_dir + '/' + cpu.filename,
                           file_template % vars())
 
+    # The variable names here are hacky, but this will creat local variables
+    # which will be referenced in vars() which have the value of the globals.
+    global maxInstSrcRegs
+    MaxInstSrcRegs = maxInstSrcRegs
+    global maxInstDestRegs
+    MaxInstDestRegs = maxInstDestRegs
+    # max_inst_regs.hh
+    update_if_needed(output_dir + '/max_inst_regs.hh', \
+            max_inst_regs_template % vars())
+
 # global list of CpuModel objects (see cpu_models.py)
 cpu_models = []