arch-riscv: Fix disassembling for fence and fence.i

[gem5.git] / src / arch / micro_asm_test.py

diff --git a/src/arch/micro_asm_test.py b/src/arch/micro_asm_test.py
index 816a74b71ef566b60ebecc6445459da88e7eb55e..e5755f717a4a3e796d74bcaf012672ea0be00ac7 100755 (executable)
--- a/src/arch/micro_asm_test.py
+++ b/src/arch/micro_asm_test.py
@@ -26,7 +26,9 @@
 #
 # Authors: Gabe Black
 
-from micro_asm import MicroAssembler, Macroop, Rom
+from __future__ import print_function
+
+from micro_asm import MicroAssembler, Combinational_Macroop, Rom_Macroop, Rom
 
 class Bah(object):
     def __init__(self):
@@ -52,20 +54,23 @@ microops = {
     "dah": Dah
 }
 
-class TestMacroop(Macroop):
+class TestMacroop(Combinational_Macroop):
     def tweak(self):
         microops["bah"] = Bah_Tweaked
     def untweak(self):
         microops["bah"] = Bah
+    def print_debug(self, message):
+        print(message)
 
     def __init__(self, name):
         super(TestMacroop, self).__init__(name)
         self.directives = {
             "tweak": self.tweak,
-            "untweak": self.untweak
+            "untweak": self.untweak,
+            "print": self.print_debug
         }
 
-assembler = MicroAssembler(TestMacroop, microops, Rom('main ROM'))
+assembler = MicroAssembler(TestMacroop, microops, Rom('main ROM'), Rom_Macroop)
 
 testAssembly = '''
 # Single line comment
@@ -82,11 +87,19 @@ def macroop squishy {
     .tweak
     bah
     .untweak
+    .print "In the midst"
     bah
     dah # single line comment after something
     .tweak
 };
 
+#Extending the rom...
+def rom
+{
+    #Here's more stuff for the rom
+    bah
+};
+
 def macroop squashy {
     bah
 };