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sim: Move the BaseTLB to src/arch/generic/
[gem5.git]
/
src
/
arch
/
mips
/
MipsInterrupts.py
diff --git
a/src/arch/mips/MipsInterrupts.py
b/src/arch/mips/MipsInterrupts.py
index 06cd54263751f83b76ffb94c6dfc6e6ca88dbf7e..9cde5daef6c3dfda8eff2c1840527dce57faacfd 100644
(file)
--- a/
src/arch/mips/MipsInterrupts.py
+++ b/
src/arch/mips/MipsInterrupts.py
@@
-31,3
+31,4
@@
from m5.SimObject import SimObject
class MipsInterrupts(SimObject):
type = 'MipsInterrupts'
cxx_class = 'MipsISA::Interrupts'
+ cxx_header = 'arch/mips/interrupts.hh'