sim: Move the BaseTLB to src/arch/generic/

[gem5.git] / src / arch / mips / MipsTLB.py

diff --git a/src/arch/mips/MipsTLB.py b/src/arch/mips/MipsTLB.py
index d06a0e7ddae5eb2f42a5cd607881f37563608c93..c43cee717953f4b35dd27b34347842da2ec68e77 100644 (file)
--- a/src/arch/mips/MipsTLB.py
+++ b/src/arch/mips/MipsTLB.py
@@ -27,31 +27,15 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
 # Authors: Jaidev Patwardhan
+#          Korey Sewell
 
 from m5.SimObject import SimObject
 from m5.params import *
 
-class MipsTLB(SimObject):
-    abstract = True
-    type = 'MipsTLB'
-    cxx_namespace = 'MipsISA'
-    cxx_class = 'TLB'
-    size = Param.Int("TLB size")
-
-class MipsDTB(MipsTLB):
-    type = 'MipsDTB'
-    cxx_namespace = 'MipsISA'
-    cxx_class = 'DTB'
-    size = 64
+from BaseTLB import BaseTLB
 
-class MipsITB(MipsTLB):
-    type = 'MipsITB'
-    cxx_namespace = 'MipsISA'
-    cxx_class = 'ITB'
-    size = 64
-
-class MipsUTB(MipsTLB):
-    type = 'MipsUTB'
-    cxx_namespace = 'MipsISA'
-    cxx_class = 'UTB'
-    size = 64
+class MipsTLB(BaseTLB):
+    type = 'MipsTLB'
+    cxx_class = 'MipsISA::TLB'
+    cxx_header = 'arch/mips/tlb.hh'
+    size = Param.Int(64, "TLB size")