X86: Use IsSquashAfter if an instruction could affect fetch translation.

[gem5.git] / src / arch / mips / SConscript

diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript
index 1b746d8b0dfcaee01e42dbd0e9715a43403a7c58..46c0dd914c3272eee74ab5f48ef81d2d254df440 100644 (file)
--- a/src/arch/mips/SConscript
+++ b/src/arch/mips/SConscript
@@ -1,6 +1,6 @@
 # -*- mode:python -*-
 
-# Copyright (c) 2007 MIPS Technologies, Inc.
+# Copyright (c) 2004-2006 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -34,27 +34,25 @@ Import('*')
 
 if env['TARGET_ISA'] == 'mips':
     Source('faults.cc')
-    Source('regfile/int_regfile.cc')
-    Source('regfile/float_regfile.cc')
-    Source('regfile/misc_regfile.cc')
-    Source('regfile/regfile.cc')
+    Source('isa.cc')
     Source('tlb.cc')
     Source('pagetable.cc')
     Source('utility.cc')
     Source('dsp.cc')
 
     SimObject('MipsTLB.py')
-    TraceFlag('MipsPRA')
+    DebugFlag('MipsPRA')
 
     if env['FULL_SYSTEM']:
-       SimObject('MipsSystem.py')
+        SimObject('MipsSystem.py')
+        SimObject('MipsInterrupts.py')
         Source('idle_event.cc')
         Source('mips_core_specific.cc')
         Source('vtophys.cc')
         Source('system.cc')
         Source('stacktrace.cc')
         Source('linux/system.cc')
-       Source('interrupts.cc')
+        Source('interrupts.cc')
         Source('bare_iron/system.cc')
     else:
         Source('process.cc')