# -*- mode:python -*-
-# Copyright (c) 2004-2005 The Regents of The University of Michigan
+# Copyright (c) 2004-2006 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
if env['TARGET_ISA'] == 'mips':
Source('faults.cc')
- Source('regfile/int_regfile.cc')
- Source('regfile/misc_regfile.cc')
- Source('regfile/regfile.cc')
+ Source('isa.cc')
+ Source('tlb.cc')
+ Source('pagetable.cc')
Source('utility.cc')
Source('dsp.cc')
+ SimObject('MipsTLB.py')
+ DebugFlag('MipsPRA')
+
if env['FULL_SYSTEM']:
- #Insert Full-System Files Here
- pass
+ SimObject('MipsSystem.py')
+ SimObject('MipsInterrupts.py')
+ Source('idle_event.cc')
+ Source('mips_core_specific.cc')
+ Source('vtophys.cc')
+ Source('system.cc')
+ Source('stacktrace.cc')
+ Source('linux/system.cc')
+ Source('interrupts.cc')
+ Source('bare_iron/system.cc')
else:
Source('process.cc')
-
Source('linux/linux.cc')
Source('linux/process.cc')