if env['TARGET_ISA'] == 'mips':
Source('faults.cc')
- Source('regfile/int_regfile.cc')
- Source('regfile/float_regfile.cc')
- Source('regfile/misc_regfile.cc')
- Source('regfile/regfile.cc')
+ Source('isa.cc')
Source('tlb.cc')
Source('pagetable.cc')
Source('utility.cc')
Source('dsp.cc')
SimObject('MipsTLB.py')
- TraceFlag('MipsPRA')
+ DebugFlag('MipsPRA')
if env['FULL_SYSTEM']:
- SimObject('MipsSystem.py')
+ SimObject('MipsSystem.py')
+ SimObject('MipsInterrupts.py')
Source('idle_event.cc')
Source('mips_core_specific.cc')
Source('vtophys.cc')
Source('system.cc')
Source('stacktrace.cc')
Source('linux/system.cc')
- Source('interrupts.cc')
+ Source('interrupts.cc')
Source('bare_iron/system.cc')
else:
Source('process.cc')