#ifndef __ARCH_MIPS_DECODER_HH__
#define __ARCH_MIPS_DECODER_HH__
-#include "arch/generic/decoder.hh"
+#include "arch/generic/decode_cache.hh"
+#include "arch/mips/types.hh"
+#include "base/misc.hh"
+#include "base/types.hh"
+#include "cpu/static_inst.hh"
namespace MipsISA
{
-class Decoder : public GenericISA::Decoder
-{};
+class Decoder
+{
+ protected:
+ //The extended machine instruction being generated
+ ExtMachInst emi;
+ bool instDone;
+
+ public:
+ Decoder() : instDone(false)
+ {}
+
+ void
+ process()
+ {
+ }
+
+ void
+ reset()
+ {
+ instDone = false;
+ }
+
+ //Use this to give data to the decoder. This should be used
+ //when there is control flow.
+ void
+ moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
+ {
+ emi = inst;
+ instDone = true;
+ }
+
+ bool
+ needMoreBytes()
+ {
+ return true;
+ }
+
+ bool
+ instReady()
+ {
+ return instDone;
+ }
+
+ void takeOverFrom(Decoder *old) {}
+
+ protected:
+ /// A cache of decoded instruction objects.
+ static GenericISA::BasicDecodeCache defaultCache;
+
+ public:
+ StaticInstPtr decodeInst(ExtMachInst mach_inst);
+
+ /// Decode a machine instruction.
+ /// @param mach_inst The binary instruction to decode.
+ /// @retval A pointer to the corresponding StaticInst object.
+ StaticInstPtr
+ decode(ExtMachInst mach_inst, Addr addr)
+ {
+ return defaultCache.decode(this, mach_inst, addr);
+ }
+
+ StaticInstPtr
+ decode(MipsISA::PCState &nextPC)
+ {
+ if (!instDone)
+ return NULL;
+ instDone = false;
+ return decode(emi, nextPC.instAddr());
+ }
+};
} // namespace MipsISA