cpu: Add CPU support for generatig wake up events when LLSC adresses are snooped.

[gem5.git] / src / arch / mips / decoder.hh

diff --git a/src/arch/mips/decoder.hh b/src/arch/mips/decoder.hh
index 071b188ae2c1e64d6403e8f522219019cd9f9601..a3a68ad07477be87aef7b7befb07a4cee8c5e8e9 100644 (file)
--- a/src/arch/mips/decoder.hh
+++ b/src/arch/mips/decoder.hh
@@ -31,13 +31,85 @@
 #ifndef __ARCH_MIPS_DECODER_HH__
 #define __ARCH_MIPS_DECODER_HH__
 
-#include "arch/generic/decoder.hh"
+#include "arch/generic/decode_cache.hh"
+#include "arch/mips/types.hh"
+#include "base/misc.hh"
+#include "base/types.hh"
+#include "cpu/static_inst.hh"
 
 namespace MipsISA
 {
 
-class Decoder : public GenericISA::Decoder
-{};
+class Decoder
+{
+  protected:
+    //The extended machine instruction being generated
+    ExtMachInst emi;
+    bool instDone;
+
+  public:
+    Decoder() : instDone(false)
+    {}
+
+    void
+    process()
+    {
+    }
+
+    void
+    reset()
+    {
+        instDone = false;
+    }
+
+    //Use this to give data to the decoder. This should be used
+    //when there is control flow.
+    void
+    moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
+    {
+        emi = inst;
+        instDone = true;
+    }
+
+    bool
+    needMoreBytes()
+    {
+        return true;
+    }
+
+    bool
+    instReady()
+    {
+        return instDone;
+    }
+
+    void takeOverFrom(Decoder *old) {}
+
+  protected:
+    /// A cache of decoded instruction objects.
+    static GenericISA::BasicDecodeCache defaultCache;
+
+  public:
+    StaticInstPtr decodeInst(ExtMachInst mach_inst);
+
+    /// Decode a machine instruction.
+    /// @param mach_inst The binary instruction to decode.
+    /// @retval A pointer to the corresponding StaticInst object.
+    StaticInstPtr
+    decode(ExtMachInst mach_inst, Addr addr)
+    {
+        return defaultCache.decode(this, mach_inst, addr);
+    }
+
+    StaticInstPtr
+    decode(MipsISA::PCState &nextPC)
+    {
+        if (!instDone)
+            return NULL;
+        instDone = false;
+        return decode(emi, nextPC.instAddr());
+    }
+};
 
 } // namespace MipsISA