cpu: Add CPU support for generatig wake up events when LLSC adresses are snooped.

[gem5.git] / src / arch / mips / dsp.cc

diff --git a/src/arch/mips/dsp.cc b/src/arch/mips/dsp.cc
index fc3ae65d6fa57f6240857db2aa8a4e6c83abcead..3f6c6866e3c7afab2470a8adf5b4c429b2eb6d8f 100755 (executable)
--- a/src/arch/mips/dsp.cc
+++ b/src/arch/mips/dsp.cc
@@ -28,13 +28,12 @@
  * Authors: Brett Miller
  */
 
-#include "arch/mips/isa_traits.hh"
 #include "arch/mips/dsp.hh"
-#include "config/full_system.hh"
-#include "cpu/static_inst.hh"
-#include "sim/serialize.hh"
+#include "arch/mips/isa_traits.hh"
 #include "base/bitfield.hh"
 #include "base/misc.hh"
+#include "cpu/static_inst.hh"
+#include "sim/serialize.hh"
 
 using namespace MipsISA;
 using namespace std;
@@ -463,6 +462,8 @@ MipsISA::dspMuleq(int32_t a, int32_t b, int32_t mode, uint32_t *dspctl)
     uint64_t b_values[SIMD_MAX_VALS];
     uint64_t c_values[SIMD_MAX_VALS];
 
+    memset(c_values, 0, sizeof(c_values));
+
     simdUnpack(a, a_values, SIMD_FMT_PH, SIGNED);
     simdUnpack(b, b_values, SIMD_FMT_PH, SIGNED);
 
@@ -743,7 +744,7 @@ MipsISA::dspMulsaq(int64_t dspac, int32_t a, int32_t b, int32_t ac,
     int nvals = SIMD_NVALS[fmt];
     uint64_t a_values[SIMD_MAX_VALS];
     uint64_t b_values[SIMD_MAX_VALS];
-    int64_t temp[2];
+    int64_t temp[2] = {0, 0};
     uint32_t ouflag = 0;
 
     simdUnpack(a, a_values, fmt, SIGNED);
@@ -923,10 +924,10 @@ MipsISA::dspPrecrqu(int32_t a, int32_t b, uint32_t *dspctl)
 
     for (int i = 0; i<2; i++) {
         r_values[i] =
-            dspSaturate((int64_t)b_values[i] >> SIMD_NBITS[SIMD_FMT_QB] - 1,
+            dspSaturate((int64_t)b_values[i] >> (SIMD_NBITS[SIMD_FMT_QB] - 1),
                         SIMD_FMT_QB, UNSIGNED, &ouflag);
         r_values[i + 2] =
-            dspSaturate((int64_t)a_values[i] >> SIMD_NBITS[SIMD_FMT_QB] - 1,
+            dspSaturate((int64_t)a_values[i] >> (SIMD_NBITS[SIMD_FMT_QB] - 1),
                         SIMD_FMT_QB, UNSIGNED, &ouflag);
     }