cpu: Add CPU support for generatig wake up events when LLSC adresses are snooped.

[gem5.git] / src / arch / mips / faults.cc

diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc
index 3076e0afe7e6c8ef60e43141ced4b9e60138ca24..3697601dc7f10f81832bda6ee1a9ca0adc81c96e 100644 (file)
--- a/src/arch/mips/faults.cc
+++ b/src/arch/mips/faults.cc
@@ -95,7 +95,7 @@ template <> FaultVals MipsFault<TlbInvalidFault>::vals =
 template <> FaultVals MipsFault<TlbRefillFault>::vals =
     { "TLB Refill Exception", 0x180, ExcCodeDummy };
 
-template <> FaultVals MipsFault<TlbModifiedFault>::vals =
+template <> MipsFaultBase::FaultVals MipsFault<TlbModifiedFault>::vals =
     { "TLB Modified Exception", 0x180, ExcCodeMod };
 
 void