cpu: Add CPU support for generatig wake up events when LLSC adresses are snooped.

[gem5.git] / src / arch / mips / faults.cc

diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc
index 9ec93f3fedc81454c53f6269fc16d58667043f67..3697601dc7f10f81832bda6ee1a9ca0adc81c96e 100644 (file)
--- a/src/arch/mips/faults.cc
+++ b/src/arch/mips/faults.cc
@@ -29,6 +29,8 @@
  * Authors: Gabe Black
  *          Korey Sewell
  *          Jaidev Patwardhan
+ *          Zhengxing Li
+ *          Deyuan Guo
  */
 
 #include "arch/mips/faults.hh"
@@ -37,11 +39,8 @@
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "debug/MipsPRA.hh"
-
-#if !FULL_SYSTEM
 #include "mem/page_table.hh"
 #include "sim/process.hh"
-#endif
 
 namespace MipsISA
 {
@@ -96,7 +95,7 @@ template <> FaultVals MipsFault<TlbInvalidFault>::vals =
 template <> FaultVals MipsFault<TlbRefillFault>::vals =
     { "TLB Refill Exception", 0x180, ExcCodeDummy };
 
-template <> FaultVals MipsFault<TlbModifiedFault>::vals =
+template <> MipsFaultBase::FaultVals MipsFault<TlbModifiedFault>::vals =
     { "TLB Modified Exception", 0x180, ExcCodeMod };
 
 void
@@ -121,7 +120,7 @@ MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
     DPRINTF(MipsPRA, "PC: %s\n", pc);
     bool delay_slot = pc.pc() + sizeof(MachInst) != pc.npc();
     tc->setMiscRegNoEffect(MISCREG_EPC,
-            pc.pc() - delay_slot ? sizeof(MachInst) : 0);
+            pc.pc() - (delay_slot ? sizeof(MachInst) : 0));
 
     // Set Cause_EXCCODE field
     CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
@@ -134,7 +133,7 @@ MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
 void
 MipsFaultBase::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
-    if (FULL_SYSTEM) {
+    if (FullSystem) {
         DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
         setExceptionState(tc, code());
         tc->pcState(vect(tc));
@@ -146,7 +145,7 @@ MipsFaultBase::invoke(ThreadContext *tc, StaticInstPtr inst)
 void
 ResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
-    if (FULL_SYSTEM) {
+    if (FullSystem) {
         DPRINTF(MipsPRA, "%s encountered.\n", name());
         /* All reset activity must be invoked from here */
         Addr handler = vect(tc);