/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Authors: Gabe Black
* Korey Sewell
+ * Jaidev Patwardhan
+ * Zhengxing Li
+ * Deyuan Guo
*/
#include "arch/mips/faults.hh"
-#include "cpu/thread_context.hh"
-#include "cpu/base.hh"
+#include "arch/mips/pra_constants.hh"
#include "base/trace.hh"
-
-#if !FULL_SYSTEM
-#include "sim/process.hh"
+#include "cpu/base.hh"
+#include "cpu/thread_context.hh"
+#include "debug/MipsPRA.hh"
#include "mem/page_table.hh"
-#endif
+#include "sim/process.hh"
namespace MipsISA
{
-FaultName MachineCheckFault::_name = "Machine Check";
-FaultVect MachineCheckFault::_vect = 0x0401;
-FaultStat MachineCheckFault::_count;
+typedef MipsFaultBase::FaultVals FaultVals;
+
+template <> FaultVals MipsFault<SystemCallFault>::vals =
+ { "Syscall", 0x180, ExcCodeSys };
-FaultName AlignmentFault::_name = "Alignment";
-FaultVect AlignmentFault::_vect = 0x0301;
-FaultStat AlignmentFault::_count;
+template <> FaultVals MipsFault<ReservedInstructionFault>::vals =
+ { "Reserved Instruction Fault", 0x180, ExcCodeRI };
-FaultName ResetFault::_name = "reset";
-FaultVect ResetFault::_vect = 0x0001;
-FaultStat ResetFault::_count;
+template <> FaultVals MipsFault<ThreadFault>::vals =
+ { "Thread Fault", 0x180, ExcCodeDummy };
-FaultName ArithmeticFault::_name = "arith";
-FaultVect ArithmeticFault::_vect = 0x0501;
-FaultStat ArithmeticFault::_count;
+template <> FaultVals MipsFault<IntegerOverflowFault>::vals =
+ { "Integer Overflow Exception", 0x180, ExcCodeOv };
-FaultName InterruptFault::_name = "interrupt";
-FaultVect InterruptFault::_vect = 0x0101;
-FaultStat InterruptFault::_count;
+template <> FaultVals MipsFault<TrapFault>::vals =
+ { "Trap", 0x180, ExcCodeTr };
-FaultName NDtbMissFault::_name = "dtb_miss_single";
-FaultVect NDtbMissFault::_vect = 0x0201;
-FaultStat NDtbMissFault::_count;
+template <> FaultVals MipsFault<BreakpointFault>::vals =
+ { "Breakpoint", 0x180, ExcCodeBp };
-FaultName PDtbMissFault::_name = "dtb_miss_double";
-FaultVect PDtbMissFault::_vect = 0x0281;
-FaultStat PDtbMissFault::_count;
+template <> FaultVals MipsFault<DspStateDisabledFault>::vals =
+ { "DSP Disabled Fault", 0x180, ExcCodeDummy };
-FaultName DtbPageFault::_name = "dfault";
-FaultVect DtbPageFault::_vect = 0x0381;
-FaultStat DtbPageFault::_count;
+template <> FaultVals MipsFault<MachineCheckFault>::vals =
+ { "Machine Check", 0x180, ExcCodeMCheck };
-FaultName DtbAcvFault::_name = "dfault";
-FaultVect DtbAcvFault::_vect = 0x0381;
-FaultStat DtbAcvFault::_count;
+template <> FaultVals MipsFault<ResetFault>::vals =
+ { "Reset Fault", 0x000, ExcCodeDummy };
-FaultName ItbMissFault::_name = "itbmiss";
-FaultVect ItbMissFault::_vect = 0x0181;
-FaultStat ItbMissFault::_count;
+template <> FaultVals MipsFault<SoftResetFault>::vals =
+ { "Soft Reset Fault", 0x000, ExcCodeDummy };
-FaultName ItbPageFault::_name = "itbmiss";
-FaultVect ItbPageFault::_vect = 0x0181;
-FaultStat ItbPageFault::_count;
+template <> FaultVals MipsFault<NonMaskableInterrupt>::vals =
+ { "Non Maskable Interrupt", 0x000, ExcCodeDummy };
-FaultName ItbAcvFault::_name = "iaccvio";
-FaultVect ItbAcvFault::_vect = 0x0081;
-FaultStat ItbAcvFault::_count;
+template <> FaultVals MipsFault<CoprocessorUnusableFault>::vals =
+ { "Coprocessor Unusable Fault", 0x180, ExcCodeCpU };
-FaultName UnimplementedOpcodeFault::_name = "opdec";
-FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
-FaultStat UnimplementedOpcodeFault::_count;
+template <> FaultVals MipsFault<InterruptFault>::vals =
+ { "Interrupt", 0x000, ExcCodeInt };
-FaultName FloatEnableFault::_name = "fen";
-FaultVect FloatEnableFault::_vect = 0x0581;
-FaultStat FloatEnableFault::_count;
+template <> FaultVals MipsFault<AddressErrorFault>::vals =
+ { "Address Error", 0x180, ExcCodeDummy };
-FaultName PalFault::_name = "pal";
-FaultVect PalFault::_vect = 0x2001;
-FaultStat PalFault::_count;
+template <> FaultVals MipsFault<TlbInvalidFault>::vals =
+ { "Invalid TLB Entry Exception", 0x180, ExcCodeDummy };
-FaultName IntegerOverflowFault::_name = "intover";
-FaultVect IntegerOverflowFault::_vect = 0x0501;
-FaultStat IntegerOverflowFault::_count;
+template <> FaultVals MipsFault<TlbRefillFault>::vals =
+ { "TLB Refill Exception", 0x180, ExcCodeDummy };
+
+template <> MipsFaultBase::FaultVals MipsFault<TlbModifiedFault>::vals =
+ { "TLB Modified Exception", 0x180, ExcCodeMod };
+
+void
+MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
+{
+ // modify SRS Ctl - Save CSS, put ESS into CSS
+ StatusReg status = tc->readMiscReg(MISCREG_STATUS);
+ if (status.exl != 1 && status.bev != 1) {
+ // SRS Ctl is modified only if Status_EXL and Status_BEV are not set
+ SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL);
+ srsCtl.pss = srsCtl.css;
+ srsCtl.css = srsCtl.ess;
+ tc->setMiscRegNoEffect(MISCREG_SRSCTL, srsCtl);
+ }
+
+ // set EXL bit (don't care if it is already set!)
+ status.exl = 1;
+ tc->setMiscRegNoEffect(MISCREG_STATUS, status);
+
+ // write EPC
+ PCState pc = tc->pcState();
+ DPRINTF(MipsPRA, "PC: %s\n", pc);
+ bool delay_slot = pc.pc() + sizeof(MachInst) != pc.npc();
+ tc->setMiscRegNoEffect(MISCREG_EPC,
+ pc.pc() - (delay_slot ? sizeof(MachInst) : 0));
+
+ // Set Cause_EXCCODE field
+ CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
+ cause.excCode = excCode;
+ cause.bd = delay_slot ? 1 : 0;
+ cause.ce = 0;
+ tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
+}
+
+void
+MipsFaultBase::invoke(ThreadContext *tc, const StaticInstPtr &inst)
+{
+ if (FullSystem) {
+ DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
+ setExceptionState(tc, code());
+ tc->pcState(vect(tc));
+ } else {
+ panic("Fault %s encountered.\n", name());
+ }
+}
+
+void
+ResetFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
+{
+ if (FullSystem) {
+ DPRINTF(MipsPRA, "%s encountered.\n", name());
+ /* All reset activity must be invoked from here */
+ Addr handler = vect(tc);
+ tc->pcState(handler);
+ DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", handler);
+ }
+
+ // Set Coprocessor 1 (Floating Point) To Usable
+ StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
+ status.cu.cu1 = 1;
+ tc->setMiscReg(MISCREG_STATUS, status);
+}
+
+void
+SoftResetFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
+{
+ panic("Soft reset not implemented.\n");
+}
+
+void
+NonMaskableInterrupt::invoke(ThreadContext *tc, const StaticInstPtr &inst)
+{
+ panic("Non maskable interrupt not implemented.\n");
+}
} // namespace MipsISA
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