Merge with head, hopefully the last time for this batch.

[gem5.git] / src / arch / mips / faults.hh

diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh
index 912b42cde4315e4515386502b7f1aa1f3fbd6c38..98638ac9a66e5a94b40a9c173bc493683b41c2fc 100644 (file)
--- a/src/arch/mips/faults.hh
+++ b/src/arch/mips/faults.hh
@@ -40,6 +40,7 @@
 #include "cpu/thread_context.hh"
 #include "debug/MipsPRA.hh"
 #include "sim/faults.hh"
+#include "sim/full_system.hh"
 
 namespace MipsISA
 {
@@ -165,7 +166,7 @@ class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault>
             StaticInstPtr inst = StaticInst::nullStaticInstPtr)
     {
         MipsFault<CoprocessorUnusableFault>::invoke(tc, inst);
-        if (FULL_SYSTEM) {
+        if (FullSystem) {
             CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
             cause.ce = coProcID;
             tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
@@ -200,7 +201,7 @@ class AddressFault : public MipsFault<T>
             StaticInstPtr inst = StaticInst::nullStaticInstPtr)
     {
         MipsFault<T>::invoke(tc, inst);
-        if (FULL_SYSTEM)
+        if (FullSystem)
             tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr);
     }
 };
@@ -252,7 +253,7 @@ class TlbFault : public AddressFault<T>
     invoke(ThreadContext * tc,
             StaticInstPtr inst = StaticInst::nullStaticInstPtr)
     {
-        if (FULL_SYSTEM) {
+        if (FullSystem) {
             DPRINTF(MipsPRA, "Fault %s encountered.\n", this->name());
             Addr vect = this->vect(tc);
             setTlbExceptionState(tc, this->code());