sim: Move the BaseTLB to src/arch/generic/

[gem5.git] / src / arch / mips / interrupts.cc

diff --git a/src/arch/mips/interrupts.cc b/src/arch/mips/interrupts.cc
index 096aa628f895a826b98ae8afbf7e440b3b947b36..a0d9de03b10697e790e11b78e3dbde3fb2eaf882 100755 (executable)
--- a/src/arch/mips/interrupts.cc
+++ b/src/arch/mips/interrupts.cc
@@ -36,6 +36,7 @@
 #include "arch/mips/pra_constants.hh"
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
+#include "debug/Interrupt.hh"
 
 namespace MipsISA
 {
@@ -122,7 +123,7 @@ Interrupts::getInterrupt(ThreadContext * tc)
         if (status.im && cause.ip) {
             DPRINTF(Interrupt, "Interrupt! IM[7:0]=%d IP[7:0]=%d \n",
                     (unsigned)status.im, (unsigned)cause.ip);
-            return new InterruptFault;
+            return std::make_shared<InterruptFault>();
         }
     }