sim: Move the BaseTLB to src/arch/generic/

[gem5.git] / src / arch / mips / interrupts.cc

diff --git a/src/arch/mips/interrupts.cc b/src/arch/mips/interrupts.cc
index 4b1f37856c1bf4ab6957462abf519dc6c71e4315..a0d9de03b10697e790e11b78e3dbde3fb2eaf882 100755 (executable)
--- a/src/arch/mips/interrupts.cc
+++ b/src/arch/mips/interrupts.cc
@@ -36,21 +36,22 @@
 #include "arch/mips/pra_constants.hh"
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
+#include "debug/Interrupt.hh"
 
 namespace MipsISA
 {
 
 static inline uint8_t
 getCauseIP(ThreadContext *tc) {
-    CauseReg cause = tc->readMiscRegNoEffect(Cause);
+    CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
     return cause.ip;
 }
 
 static inline void
 setCauseIP(ThreadContext *tc, uint8_t val) {
-    CauseReg cause = tc->readMiscRegNoEffect(Cause);
+    CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
     cause.ip = val;
-    tc->setMiscRegNoEffect(Cause, cause);
+    tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
 }
 
 void
@@ -111,18 +112,18 @@ Interrupts::getInterrupt(ThreadContext * tc)
     DPRINTF(Interrupt, "Interrupts getInterrupt\n");
 
     //Check if there are any outstanding interrupts
-    StatusReg status = tc->readMiscRegNoEffect(Status);
+    StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
     // Interrupts must be enabled, error level must be 0 or interrupts
     // inhibited, and exception level must be 0 or interrupts inhibited
     if ((status.ie == 1) && (status.erl == 0) && (status.exl == 0)) {
         // Software interrupts & hardware interrupts are handled in software.
         // So if any interrupt that isn't masked is detected, jump to interrupt
         // handler
-        CauseReg cause = tc->readMiscRegNoEffect(Cause);
+        CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
         if (status.im && cause.ip) {
             DPRINTF(Interrupt, "Interrupt! IM[7:0]=%d IP[7:0]=%d \n",
                     (unsigned)status.im, (unsigned)cause.ip);
-            return new InterruptFault;
+            return std::make_shared<InterruptFault>();
         }
     }
 
@@ -132,8 +133,8 @@ Interrupts::getInterrupt(ThreadContext * tc)
 bool
 Interrupts::onCpuTimerInterrupt(ThreadContext * tc) const
 {
-    MiscReg compare = tc->readMiscRegNoEffect(Compare);
-    MiscReg count = tc->readMiscRegNoEffect(Count);
+    MiscReg compare = tc->readMiscRegNoEffect(MISCREG_COMPARE);
+    MiscReg count = tc->readMiscRegNoEffect(MISCREG_COUNT);
     if (compare == count && count != 0)
         return true;
     return false;
@@ -153,7 +154,7 @@ Interrupts::interruptsPending(ThreadContext *tc) const
     if (onCpuTimerInterrupt(tc)) {
         DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n");
         //determine timer interrupt IP #
-        IntCtlReg intCtl = tc->readMiscRegNoEffect(IntCtl);
+        IntCtlReg intCtl = tc->readMiscRegNoEffect(MISCREG_INTCTL);
         uint8_t intStatus = getCauseIP(tc);
         intStatus |= 1 << intCtl.ipti;
         setCauseIP(tc, intStatus);