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sim: Move the BaseTLB to src/arch/generic/
[gem5.git]
/
src
/
arch
/
mips
/
interrupts.cc
diff --git
a/src/arch/mips/interrupts.cc
b/src/arch/mips/interrupts.cc
index f4221ab2cd5f60e54cbd039edaf01a09cd916ba7..a0d9de03b10697e790e11b78e3dbde3fb2eaf882 100755
(executable)
--- a/
src/arch/mips/interrupts.cc
+++ b/
src/arch/mips/interrupts.cc
@@
-123,7
+123,7
@@
Interrupts::getInterrupt(ThreadContext * tc)
if (status.im && cause.ip) {
DPRINTF(Interrupt, "Interrupt! IM[7:0]=%d IP[7:0]=%d \n",
(unsigned)status.im, (unsigned)cause.ip);
- return
new InterruptFault
;
+ return
std::make_shared<InterruptFault>()
;
}
}