syscall_emul: [patch 13/22] add system call retry capability

[gem5.git] / src / arch / mips / isa / decoder.isa

diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 8ebfa66bf4be883aa26a881ef10e6f14417bc497..5c3c6f6b10062238c5e4729aac1ac75a2b5926b7 100644 (file)
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -163,13 +163,13 @@ decode OPCODE_HI default Unknown::unknown() {
                 format BasicOp {
                     0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
                     0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
-                    0x4: decode FULL_SYSTEM {
-                        0: syscall_se({{ xc->syscall(R2); }},
+                    0x4: decode FullSystemInt {
+                        0: syscall_se({{ xc->syscall(R2, &fault); }},
                                 IsSerializeAfter, IsNonSpeculative);
-                        default: syscall({{ fault = new SystemCallFault(); }});
+                      default: syscall({{ fault = std::make_shared<SystemCallFault>(); }});
                     }
                     0x7: sync({{ ; }}, IsMemBarrier);
-                    0x5: break({{fault = new BreakpointFault();}});
+                  0x5: break({{fault = std::make_shared<BreakpointFault>();}});
                 }
 
             }
@@ -212,18 +212,18 @@ decode OPCODE_HI default Unknown::unknown() {
                         0x0: add({{
                             IntReg result;
                             Rd = result = Rs + Rt;
-                            if (FULL_SYSTEM &&
+                            if (FullSystem &&
                                     findOverflow(32, result, Rs, Rt)) {
-                                fault = new IntegerOverflowFault();
+                                fault = std::make_shared<IntegerOverflowFault>();
                             }
                         }});
                         0x1: addu({{ Rd_sw = Rs_sw + Rt_sw;}});
                         0x2: sub({{
                             IntReg result;
                             Rd = result = Rs - Rt;
-                            if (FULL_SYSTEM &&
+                            if (FullSystem &&
                                     findOverflow(32, result, Rs, ~Rt)) {
-                                fault = new IntegerOverflowFault();
+                                fault = std::make_shared<IntegerOverflowFault>();
                             }
                         }});
                         0x3: subu({{ Rd_sw = Rs_sw - Rt_sw; }});
@@ -325,9 +325,9 @@ decode OPCODE_HI default Unknown::unknown() {
             0x0: addi({{
                 IntReg result;
                 Rt = result = Rs + imm;
-                if (FULL_SYSTEM &&
+                if (FullSystem &&
                         findOverflow(32, result, Rs, imm)) {
-                    fault = new IntegerOverflowFault();
+                    fault = std::make_shared<IntegerOverflowFault>();
                 }
             }});
             0x1: addiu({{ Rt_sw = Rs_sw + imm; }});
@@ -359,7 +359,7 @@ decode OPCODE_HI default Unknown::unknown() {
                                 Rt &= 0xFFFFE7FF;
                         }
                     }});
-                    0x4: mtc0({{ 
+                    0x4: mtc0({{
                         CP0_RD_SEL = Rt;
                         CauseReg cause = Cause;
                         IntCtlReg intCtl = IntCtl;
@@ -385,7 +385,7 @@ decode OPCODE_HI default Unknown::unknown() {
                     0x8: decode MT_U {
                         0x0: mftc0({{
                             data = xc->readRegOtherThread((RT << 3 | SEL) +
-                                                          Ctrl_Base_DepTag);
+                                                          Misc_Reg_Base);
                         }});
                         0x1: decode SEL {
                             0x0: mftgpr({{
@@ -409,19 +409,19 @@ decode OPCODE_HI default Unknown::unknown() {
                             }
                             0x2: decode MT_H {
                                 0x0: mftc1({{ data = xc->readRegOtherThread(RT +
-                                                                            FP_Base_DepTag);
+                                                                            FP_Reg_Base);
                                 }});
                                 0x1: mfthc1({{ data = xc->readRegOtherThread(RT +
-                                                                             FP_Base_DepTag);
+                                                                             FP_Reg_Base);
                                 }});
                             }
                             0x3: cftc1({{
                                 uint32_t fcsr_val = xc->readRegOtherThread(FLOATREG_FCSR +
-                                                                            FP_Base_DepTag);
+                                                                            FP_Reg_Base);
                                 switch (RT) {
                                   case 0:
                                     data = xc->readRegOtherThread(FLOATREG_FIR +
-                                                                  Ctrl_Base_DepTag);
+                                                                  Misc_Reg_Base);
                                     break;
                                   case 25:
                                     data = (fcsr_val & 0xFE000000 >> 24) |
@@ -450,7 +450,7 @@ decode OPCODE_HI default Unknown::unknown() {
                 format MT_MTTR {
                     // Decode MIPS MT MTTR instruction into sub-instructions
                     0xC: decode MT_U {
-                        0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Ctrl_Base_DepTag,
+                        0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Misc_Reg_Base,
                                                             Rt);
                                    }});
                         0x1: decode SEL {
@@ -496,10 +496,10 @@ decode OPCODE_HI default Unknown::unknown() {
                             }
                             0x2: mttc1({{
                                 uint64_t data = xc->readRegOtherThread(RD +
-                                                                       FP_Base_DepTag);
+                                                                       FP_Reg_Base);
                                 data = insertBits(data, MT_H ? 63 : 31,
                                                   MT_H ? 32 : 0, Rt);
-                                xc->setRegOtherThread(RD + FP_Base_DepTag,
+                                xc->setRegOtherThread(RD + FP_Reg_Base,
                                                       data);
                             }});
                             0x3: cttc1({{
@@ -534,7 +534,7 @@ decode OPCODE_HI default Unknown::unknown() {
                                             "Access to Floating Control "
                                             "S""tatus Register", FS);
                                 }
-                                xc->setRegOtherThread(FLOATREG_FCSR + FP_Base_DepTag, data);
+                                xc->setRegOtherThread(FLOATREG_FCSR + FP_Reg_Base, data);
                             }});
                             default: CP0Unimpl::unknown();
                         }
@@ -601,7 +601,7 @@ decode OPCODE_HI default Unknown::unknown() {
                                 } else {
                                     // Enable this else branch once we
                                     // actually set values for Config on init
-                                    fault = new ReservedInstructionFault();
+                                    fault = std::make_shared<ReservedInstructionFault>();
                                 }
                                 Status = status;
                             }});
@@ -612,7 +612,7 @@ decode OPCODE_HI default Unknown::unknown() {
                                     Rt = status;
                                     status.ie = 1;
                                 } else {
-                                    fault = new ReservedInstructionFault();
+                                    fault = std::make_shared<ReservedInstructionFault>();
                                 }
                             }});
                             default:CP0Unimpl::unknown();
@@ -627,7 +627,7 @@ decode OPCODE_HI default Unknown::unknown() {
                             // Rev 2 of the architecture
                             panic("Shadow Sets Not Fully Implemented.\n");
                         } else {
-                          fault = new ReservedInstructionFault();
+                            fault = std::make_shared<ReservedInstructionFault>();
                         }
                     }});
                     0xE: wrpgpr({{
@@ -636,7 +636,7 @@ decode OPCODE_HI default Unknown::unknown() {
                             // Rev 2 of the architecture
                             panic("Shadow Sets Not Fully Implemented.\n");
                         } else {
-                            fault = new ReservedInstructionFault();
+                            fault = std::make_shared<ReservedInstructionFault>();
                         }
                     }});
                 }
@@ -1238,12 +1238,12 @@ decode OPCODE_HI default Unknown::unknown() {
                     0x3: CP1Unimpl::unknown();
                     0x7: CP1Unimpl::unknown();
 
-                    //Table A-16 MIPS32 COP1 Encoding of Function 
+                    //Table A-16 MIPS32 COP1 Encoding of Function
                     //Field When rs=W
                     0x4: decode FUNCTION {
                         format FloatConvertOp {
-                            0x20: cvt_s_w({{ val = Fs_uw; }}, ToSingle);
-                            0x21: cvt_d_w({{ val = Fs_uw; }}, ToDouble);
+                            0x20: cvt_s_w({{ val = Fs_sw; }}, ToSingle);
+                            0x21: cvt_d_w({{ val = Fs_sw; }}, ToDouble);
                             0x26: CP1Unimpl::cvt_ps_w();
                         }
                         default: CP1Unimpl::unknown();
@@ -1255,8 +1255,8 @@ decode OPCODE_HI default Unknown::unknown() {
                     //floating point operations are enabled."
                     0x5: decode FUNCTION {
                         format FloatConvertOp {
-                            0x20: cvt_s_l({{ val = Fs_ud; }}, ToSingle);
-                            0x21: cvt_d_l({{ val = Fs_ud; }}, ToDouble);
+                            0x20: cvt_s_l({{ val = Fs_sd; }}, ToSingle);
+                            0x21: cvt_d_l({{ val = Fs_sd; }}, ToDouble);
                             0x26: CP1Unimpl::cvt_ps_l();
                         }
                         default: CP1Unimpl::unknown();
@@ -1867,7 +1867,7 @@ decode OPCODE_HI default Unknown::unknown() {
                             }});
                             0x7: precr_sra_r_ph_w({{
                                 Rt_uw = dspPrecrSra(Rt_uw, Rs_uw, RD,
-                                                    SIMD_FMT_W, ROUND); 
+                                                    SIMD_FMT_W, ROUND);
                             }});
                         }
                     }
@@ -2404,7 +2404,7 @@ decode OPCODE_HI default Unknown::unknown() {
                     0x3: decode OP_LO {
                         format DspHiLoOp {
                             0x2: shilo({{
-                                if (sext<6>(HILOSA) < 0) {
+                                        if ((int64_t)sext<6>(HILOSA) < 0) {
                                     dspac = (uint64_t)dspac <<
                                                 -sext<6>(HILOSA);
                                 } else {
@@ -2413,7 +2413,7 @@ decode OPCODE_HI default Unknown::unknown() {
                                 }
                             }});
                             0x3: shilov({{
-                                if (sext<6>(Rs_sw<5:0>) < 0) {
+                                        if ((int64_t)sext<6>(Rs_sw<5:0>) < 0) {
                                     dspac = (uint64_t)dspac <<
                                                 -sext<6>(Rs_sw<5:0>);
                                 } else {
@@ -2431,7 +2431,7 @@ decode OPCODE_HI default Unknown::unknown() {
                     }
                 }
                 0x3: decode OP default FailUnimpl::rdhwr() {
-                    0x0: decode FULL_SYSTEM {
+                    0x0: decode FullSystemInt {
                         0: decode RD {
                             29: BasicOp::rdhwr_se({{ Rt = TpValue; }});
                         }