Merge zizzer:/bk/newmem

[gem5.git] / src / arch / mips / isa / formats / branch.isa

diff --git a/src/arch/mips/isa/formats/branch.isa b/src/arch/mips/isa/formats/branch.isa
index e8843da03fe63d98b07c2a7e1e13c15ba7419d70..a67f04dca84fb6613a2b9cbc1ee7b8d6dbcb8599 100644 (file)
--- a/src/arch/mips/isa/formats/branch.isa
+++ b/src/arch/mips/isa/formats/branch.isa
@@ -1,5 +1,33 @@
 // -*- mode:c++ -*-
 
+// Copyright (c) 2006 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
+
 ////////////////////////////////////////////////////////////////////
 //
 // Control transfer instructions
@@ -8,7 +36,6 @@
 output header {{
 
 #include <iostream>
-    using namespace std;
 
     /**
      * Base class for instructions whose disassembly is not purely a
@@ -207,10 +234,11 @@ def format Branch(code,*opt_flags) {{
         else:
             inst_flags += (x, )
 
+    #Take into account uncond. branch instruction
     if 'cond == 1' in code:
-         inst_flags += ('IsCondControl', )
+         inst_flags += ('IsUnCondControl', )
     else:
-         inst_flags += ('IsUncondControl', )
+         inst_flags += ('IsCondControl', )
 
     #Condition code
     code = 'bool cond;\n' + code
@@ -219,7 +247,7 @@ def format Branch(code,*opt_flags) {{
     code += '} else {\n'
     code += not_taken_code
 
-    iop = InstObjParams(name, Name, 'Branch', CodeBlock(code), inst_flags)
+    iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
     header_output = BasicDeclare.subst(iop)
     decoder_output = BasicConstructor.subst(iop)
     decode_block = BasicDecode.subst(iop)
@@ -238,7 +266,7 @@ def format Jump(code, *opt_flags) {{
         else:
             inst_flags += (x, )
 
-    iop = InstObjParams(name, Name, 'Jump', CodeBlock(code), inst_flags)
+    iop = InstObjParams(name, Name, 'Jump', code, inst_flags)
     header_output = BasicDeclare.subst(iop)
     decoder_output = BasicConstructor.subst(iop)
     decode_block = BasicDecode.subst(iop)