Yet another merge with the main repository.

[gem5.git] / src / arch / mips / isa / formats / fp.isa

diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index 52fcd07241b46d0cec45b393229d0cd0b2825f31..63823f40459f347eed849122c3317042a64a58cf 100644 (file)
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -135,12 +135,13 @@ output exec {{
                 cpu->setFloatRegOperandBits(inst, 0, mips_nan);
 
                 //Read FCSR from FloatRegFile
-                uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR);
+                uint32_t fcsr_bits =
+                    cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR);
 
                 uint32_t new_fcsr = genInvalidVector(fcsr_bits);
 
                 //Write FCSR from FloatRegFile
-                cpu->tcBase()->setFloatRegBits(FCSR, new_fcsr);
+                cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, new_fcsr);
 
                 if (traceData) { traceData->setData(mips_nan); }
                 return true;
@@ -153,13 +154,13 @@ output exec {{
         fpResetCauseBits(%(CPU_exec_context)s *cpu)
         {
             //Read FCSR from FloatRegFile
-            uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FCSR);
+            uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR);
 
             // TODO: Use utility function here
             fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
 
             //Write FCSR from FloatRegFile
-            cpu->tcBase()->setFloatRegBits(FCSR, fcsr);
+            cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, fcsr);
         }
 }};
 
@@ -173,9 +174,8 @@ def template FloatingPointExecute {{
 
                 //When is the right time to reset cause bits?
                 //start of every instruction or every cycle?
-#if FULL_SYSTEM
-                fpResetCauseBits(xc);
-#endif
+                if (FullSystem)
+                    fpResetCauseBits(xc);
                 %(op_decl)s;
                 %(op_rd)s;
 
@@ -190,12 +190,12 @@ def template FloatingPointExecute {{
                     //----
                     //Check for IEEE 754 FP Exceptions
                     //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData);
-                    if (
-#if FULL_SYSTEM
-                        !fpInvalidOp((FPOp*)this, xc, Fd, traceData) &&
-#endif
-                        fault == NoFault)
-                    {
+                    bool invalid_op = false;
+                    if (FullSystem) {
+                        invalid_op =
+                            fpInvalidOp((FPOp*)this, xc, Fd, traceData);
+                    }
+                    if (!invalid_op && fault == NoFault) {
                         %(op_wb)s;
                     }
                 }
@@ -217,20 +217,20 @@ def format FloatCompareOp(cond_code, *flags) {{
     import sys
 
     code = 'bool cond;\n'
-    if '.sf' in cond_code or 'SinglePrecision' in flags:
+    if '_sf' in cond_code or 'SinglePrecision' in flags:
         if 'QnanException' in flags:
-            code += 'if (isQnan(&Fs.sf, 32) || isQnan(&Ft.sf, 32)) {\n'
+            code += 'if (isQnan(&Fs_sf, 32) || isQnan(&Ft_sf, 32)) {\n'
             code += '\tFCSR = genInvalidVector(FCSR);\n'
             code += '\treturn NoFault;'
             code += '}\n else '
-        code += 'if (isNan(&Fs.sf, 32) || isNan(&Ft.sf, 32)) {\n'
-    elif '.df' in cond_code or 'DoublePrecision' in flags:
+        code += 'if (isNan(&Fs_sf, 32) || isNan(&Ft_sf, 32)) {\n'
+    elif '_df' in cond_code or 'DoublePrecision' in flags:
         if 'QnanException' in flags:
-            code += 'if (isQnan(&Fs.df, 64) || isQnan(&Ft.df, 64)) {\n'
+            code += 'if (isQnan(&Fs_df, 64) || isQnan(&Ft_df, 64)) {\n'
             code += '\tFCSR = genInvalidVector(FCSR);\n'
             code += '\treturn NoFault;'
             code += '}\n else '
-        code += 'if (isNan(&Fs.df, 64) || isNan(&Ft.df, 64)) {\n'
+        code += 'if (isNan(&Fs_df, 64) || isNan(&Ft_df, 64)) {\n'
     else:
        sys.exit('Decoder Failed: Can\'t Determine Operand Type\n')
 
@@ -257,16 +257,16 @@ def format FloatConvertOp(code, *flags) {{
 
     #Determine Source Type
     convert = 'fpConvert('
-    if '.sf' in code:
+    if '_sf' in code:
         code = 'float ' + code + '\n'
         convert += 'SINGLE_TO_'
-    elif '.df' in code:
+    elif '_df' in code:
         code = 'double ' + code + '\n'
         convert += 'DOUBLE_TO_'
-    elif '.uw' in code:
+    elif '_uw' in code:
         code = 'uint32_t ' + code + '\n'
         convert += 'WORD_TO_'
-    elif '.ud' in code:
+    elif '_ud' in code:
         code = 'uint64_t ' + code + '\n'
         convert += 'LONG_TO_'
     else:
@@ -274,13 +274,13 @@ def format FloatConvertOp(code, *flags) {{
 
     #Determine Destination Type
     if 'ToSingle' in flags:
-        code += 'Fd.uw = ' + convert + 'SINGLE, '
+        code += 'Fd_uw = ' + convert + 'SINGLE, '
     elif 'ToDouble' in flags:
-        code += 'Fd.ud = ' + convert + 'DOUBLE, '
+        code += 'Fd_ud = ' + convert + 'DOUBLE, '
     elif 'ToWord' in flags:
-        code += 'Fd.uw = ' + convert + 'WORD, '
+        code += 'Fd_uw = ' + convert + 'WORD, '
     elif 'ToLong' in flags:
-        code += 'Fd.ud = ' + convert + 'LONG, '
+        code += 'Fd_ud = ' + convert + 'LONG, '
     else:
         sys.exit("Error Determining Destination Type for Conversion")
 
@@ -328,17 +328,17 @@ def format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{
     code += 'code_block1 = code_block2 = true;\n'
 
     if 'QnanException' in flags:
-        code += 'if (isQnan(&Fs1.sf, 32) || isQnan(&Ft1.sf, 32)) {\n'
+        code += 'if (isQnan(&Fs1_sf, 32) || isQnan(&Ft1_sf, 32)) {\n'
         code += '\tFCSR = genInvalidVector(FCSR);\n'
         code += 'code_block1 = false;'
         code += '}\n'
-        code += 'if (isQnan(&Fs2.sf, 32) || isQnan(&Ft2.sf, 32)) {\n'
+        code += 'if (isQnan(&Fs2_sf, 32) || isQnan(&Ft2_sf, 32)) {\n'
         code += '\tFCSR = genInvalidVector(FCSR);\n'
         code += 'code_block2 = false;'
         code += '}\n'
 
     code += 'if (code_block1) {'
-    code += '\tif (isNan(&Fs1.sf, 32) || isNan(&Ft1.sf, 32)) {\n'
+    code += '\tif (isNan(&Fs1_sf, 32) || isNan(&Ft1_sf, 32)) {\n'
     if 'UnorderedTrue' in flags:
        code += 'cond1 = 1;\n'
     elif 'UnorderedFalse' in flags:
@@ -350,7 +350,7 @@ def format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{
     code += 'FCSR = genCCVector(FCSR, CC, cond1);}\n}\n'
 
     code += 'if (code_block2) {'
-    code += '\tif (isNan(&Fs2.sf, 32) || isNan(&Ft2.sf, 32)) {\n'
+    code += '\tif (isNan(&Fs2_sf, 32) || isNan(&Ft2_sf, 32)) {\n'
     if 'UnorderedTrue' in flags:
        code += 'cond2 = 1;\n'
     elif 'UnorderedFalse' in flags: