Merge ktlim@zizzer:/bk/newmem

[gem5.git] / src / arch / mips / isa / formats / fp.isa

diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index 6647f93619f05cfb2f4068d291414340db29be90..ac6805cc736fd70904629455d053532dba993ec9 100644 (file)
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -1,5 +1,33 @@
 // -*- mode:c++ -*-
 
+// Copyright (c) 2006 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
+
 ////////////////////////////////////////////////////////////////////
 //
 // Floating Point operate instructions
@@ -71,7 +99,7 @@ output exec {{
             int size = sizeof(src_op) * 8;
 
             for (int i = 0; i < inst->numSrcRegs(); i++) {
-                uint64_t src_bits = xc->readFloatRegBits(inst, 0, size);
+                uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0, size);
 
                 if (isNan(&src_bits, size) ) {
                     if (isSnan(&src_bits, size)) {
@@ -85,7 +113,7 @@ output exec {{
                         mips_nan = src_bits;
                     }
 
-                    xc->setFloatRegBits(inst, 0, mips_nan, size);
+                    xc->setFloatRegOperandBits(inst, 0, mips_nan, size);
                     if (traceData) { traceData->setData(mips_nan); }
                     return true;
                 }
@@ -95,7 +123,7 @@ output exec {{
 
         template <class T>
         bool
-        fpInvalidOp(FPOp *inst, %(CPU_exec_context)s *xc, const T dest_val,
+        fpInvalidOp(FPOp *inst, %(CPU_exec_context)s *cpu, const T dest_val,
                     Trace::InstRecord *traceData)
         {
             uint64_t mips_nan = 0;
@@ -111,13 +139,13 @@ output exec {{
                 }
 
                 //Set value to QNAN
-                xc->setFloatRegBits(inst, 0, mips_nan, size);
+                cpu->setFloatRegOperandBits(inst, 0, mips_nan, size);
 
                 //Read FCSR from FloatRegFile
-                uint32_t fcsr_bits = xc->cpuXC->readFloatRegBits(FCSR);
+                uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR);
 
                 //Write FCSR from FloatRegFile
-                xc->cpuXC->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits));
+                cpu->tcBase()->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits));
 
                 if (traceData) { traceData->setData(mips_nan); }
                 return true;
@@ -127,15 +155,15 @@ output exec {{
         }
 
         void
-        fpResetCauseBits(%(CPU_exec_context)s *xc)
+        fpResetCauseBits(%(CPU_exec_context)s *cpu)
         {
             //Read FCSR from FloatRegFile
-            uint32_t fcsr = xc->cpuXC->readFloatRegBits(FCSR);
+            uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FCSR);
 
             fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
 
             //Write FCSR from FloatRegFile
-            xc->cpuXC->setFloatRegBits(FCSR, fcsr);
+            cpu->tcBase()->setFloatRegBits(FCSR, fcsr);
         }
 }};
 
@@ -148,8 +176,9 @@ def template FloatingPointExecute {{
 
                 //When is the right time to reset cause bits?
                 //start of every instruction or every cycle?
+#if FULL_SYSTEM
                 fpResetCauseBits(xc);
-
+#endif
                 %(op_decl)s;
                 %(op_rd)s;
 
@@ -164,7 +193,10 @@ def template FloatingPointExecute {{
                     //----
                     //Check for IEEE 754 FP Exceptions
                     //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData);
-                    if (!fpInvalidOp((FPOp*)this, xc, Fd, traceData) &&
+                    if (
+#if FULL_SYSTEM
+                        !fpInvalidOp((FPOp*)this, xc, Fd, traceData) &&
+#endif
                         fault == NoFault)
                     {
                         %(op_wb)s;
@@ -177,7 +209,7 @@ def template FloatingPointExecute {{
 
 // Primary format for float point operate instructions:
 def format FloatOp(code, *flags) {{
-        iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code), flags)
+        iop = InstObjParams(name, Name, 'FPOp', code, flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
         decode_block = BasicDecode.subst(iop)
@@ -216,7 +248,7 @@ def format FloatCompareOp(cond_code, *flags) {{
     code +=  cond_code + '}'
     code += 'FCSR = genCCVector(FCSR, CC, cond);\n'
 
-    iop = InstObjParams(name, Name, 'FPCompareOp', CodeBlock(code))
+    iop = InstObjParams(name, Name, 'FPCompareOp', code)
     header_output = BasicDeclare.subst(iop)
     decoder_output = BasicConstructor.subst(iop)
     decode_block = BasicDecode.subst(iop)
@@ -267,7 +299,7 @@ def format FloatConvertOp(code, *flags) {{
     else:
         code += 'val); '
 
-    iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code))
+    iop = InstObjParams(name, Name, 'FPOp', code)
     header_output = BasicDeclare.subst(iop)
     decoder_output = BasicConstructor.subst(iop)
     decode_block = BasicDecode.subst(iop)
@@ -275,7 +307,7 @@ def format FloatConvertOp(code, *flags) {{
 }};
 
 def format FloatAccOp(code, *flags) {{
-        iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code), flags)
+        iop = InstObjParams(name, Name, 'FPOp', code, flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
         decode_block = BasicDecode.subst(iop)
@@ -284,7 +316,7 @@ def format FloatAccOp(code, *flags) {{
 
 // Primary format for float64 operate instructions:
 def format Float64Op(code, *flags) {{
-        iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
+        iop = InstObjParams(name, Name, 'MipsStaticInst', code, flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
         decode_block = BasicDecode.subst(iop)
@@ -332,7 +364,7 @@ def format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{
     code +=  cond_code2
     code += 'FCSR = genCCVector(FCSR, CC, cond2);}\n}'
 
-    iop = InstObjParams(name, Name, 'FPCompareOp', CodeBlock(code))
+    iop = InstObjParams(name, Name, 'FPCompareOp', code)
     header_output = BasicDeclare.subst(iop)
     decoder_output = BasicConstructor.subst(iop)
     decode_block = BasicDecode.subst(iop)