// -*- mode:c++ -*-
+// Copyright \e.A\eN) 2007 MIPS Technologies, Inc. All Rights Reserved
+
+// This software is part of the M5 simulator.
+
+// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
+// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+// TO THESE TERMS AND CONDITIONS.
+
+// Permission is granted to use, copy, create derivative works and
+// distribute this software and such derivative works for any purpose,
+// so long as (1) the copyright notice above, this grant of permission,
+// and the disclaimer below appear in all copies and derivative works
+// made, (2) the copyright notice above is augmented as appropriate to
+// reflect the addition of any new copyrightable work in a derivative
+// work (e.g., Copyright
\e.A
\eN) <Publication Year> Copyright Owner), and (3)
+// the name of MIPS Technologies, Inc. (\e$B!H\e(BMIPS\e$B!I\e(B) is not used in any
+// advertising or publicity pertaining to the use or distribution of
+// this software without specific, written prior authorization.
+
+// THIS SOFTWARE IS PROVIDED \e$B!H\e(BAS IS.\e$B!I\e(B MIPS MAKES NO WARRANTIES AND
+// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
+
////////////////////////////////////////////////////////////////////
//
// Integer operate instructions
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
- class HiLoMiscOp: public HiLoOp
+ class HiLoRsSelOp: public HiLoOp
+ {
+ protected:
+
+ /// Constructor
+ HiLoRsSelOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+ HiLoOp(mnem, _machInst, __opClass)
+ {
+ }
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+
+ class HiLoRdSelOp: public HiLoOp
{
protected:
/// Constructor
- HiLoMiscOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+ HiLoRdSelOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
HiLoOp(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
+ class HiLoRdSelValOp: public HiLoOp
+ {
+ protected:
+
+ /// Constructor
+ HiLoRdSelValOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+ HiLoOp(mnem, _machInst, __opClass)
+ {
+ }
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
class IntImmOp : public MipsStaticInst
{
}};
-// HiLo<Misc> instruction class execute method template.
-// Mainly to get instruction trace data to print out
-// correctly
+// HiLo instruction class execute method template.
def template HiLoExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
{
if(fault == NoFault)
{
%(op_wb)s;
- //If there are 2 Destination Registers then
- //concatenate the values for the traceData
- if(traceData && _numDestRegs == 2) {
- uint64_t hilo_final_val = (uint64_t)HI << 32 | LO;
- traceData->setData(hilo_final_val);
- }
+ }
+ return fault;
+ }
+}};
+
+// HiLoRsSel instruction class execute method template.
+def template HiLoRsSelExecute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+ {
+ Fault fault = NoFault;
+
+ %(op_decl)s;
+
+ if( ACSRC > 0 && !isDspEnabled(xc) )
+ {
+ fault = new DspStateDisabledFault();
+ }
+ else
+ {
+ %(op_rd)s;
+ %(code)s;
+ }
+
+ if(fault == NoFault)
+ {
+ %(op_wb)s;
+ }
+ return fault;
+ }
+}};
+
+// HiLoRdSel instruction class execute method template.
+def template HiLoRdSelExecute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+ {
+ Fault fault = NoFault;
+
+ %(op_decl)s;
+
+ if( ACDST > 0 && !isDspEnabled(xc) )
+ {
+ fault = new DspStateDisabledFault();
+ }
+ else
+ {
+ %(op_rd)s;
+ %(code)s;
+ }
+
+ if(fault == NoFault)
+ {
+ %(op_wb)s;
}
return fault;
}
return ss.str();
}
- std::string HiLoMiscOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ std::string HiLoRsSelOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ std::stringstream ss;
+
+ ccprintf(ss, "%-10s ", mnemonic);
+
+ if (_numDestRegs > 0 && _destRegIdx[0] < 32) {
+ printReg(ss, _destRegIdx[0]);
+ } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) {
+ printReg(ss, _srcRegIdx[0]);
+ }
+
+ return ss.str();
+ }
+
+ std::string HiLoRdSelOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ std::stringstream ss;
+
+ ccprintf(ss, "%-10s ", mnemonic);
+
+ if (_numDestRegs > 0 && _destRegIdx[0] < 32) {
+ printReg(ss, _destRegIdx[0]);
+ } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) {
+ printReg(ss, _srcRegIdx[0]);
+ }
+
+ return ss.str();
+ }
+
+ std::string HiLoRdSelValOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
}};
def format IntOp(code, *opt_flags) {{
- iop = InstObjParams(name, Name, 'IntOp', CodeBlock(code), opt_flags)
+ iop = InstObjParams(name, Name, 'IntOp', code, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
- decode_block = OperateNopCheckDecode.subst(iop)
+ decode_block = RegNopCheckDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
}};
def format IntImmOp(code, *opt_flags) {{
- iop = InstObjParams(name, Name, 'IntImmOp', CodeBlock(code), opt_flags)
+ iop = InstObjParams(name, Name, 'IntImmOp', code, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
- decode_block = OperateNopCheckDecode.subst(iop)
+ decode_block = ImmNopCheckDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
}};
-def format HiLoOp(code, *opt_flags) {{
+def format HiLoRsSelOp(code, *opt_flags) {{
+ iop = InstObjParams(name, Name, 'HiLoRsSelOp', code, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = HiLoRsSelExecute.subst(iop)
+}};
+
+def format HiLoRdSelOp(code, *opt_flags) {{
+ iop = InstObjParams(name, Name, 'HiLoRdSelOp', code, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = HiLoRdSelExecute.subst(iop)
+}};
+
+def format HiLoRdSelValOp(code, *opt_flags) {{
+
if '.sd' in code:
code = 'int64_t ' + code
elif '.ud' in code:
code = 'uint64_t ' + code
- code += 'HI = val<63:32>;\n'
- code += 'LO = val<31:0>;\n'
+ code += 'HI_RD_SEL = val<63:32>;\n'
+ code += 'LO_RD_SEL = val<31:0>;\n'
- iop = InstObjParams(name, Name, 'HiLoOp', CodeBlock(code), opt_flags)
+ iop = InstObjParams(name, Name, 'HiLoRdSelOp', code, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
- decode_block = OperateNopCheckDecode.subst(iop)
- exec_output = HiLoExecute.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = HiLoRdSelExecute.subst(iop)
}};
-def format HiLoMiscOp(code, *opt_flags) {{
- iop = InstObjParams(name, Name, 'HiLoMiscOp', CodeBlock(code), opt_flags)
+def format HiLoOp(code, *opt_flags) {{
+ iop = InstObjParams(name, Name, 'HiLoOp', code, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
- decode_block = OperateNopCheckDecode.subst(iop)
+ decode_block = BasicDecode.subst(iop)
exec_output = HiLoExecute.subst(iop)
}};
-
-
-
-
-
projects / gem5.git / blobdiff